OTP Memory Verification and Fallback Mechanism

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

One-time programmable (OTP) memories are limited to a single programming instance, which is not versatile enough for applications requiring multiple configurations, and are costly due to their physical and electrical testing features, unlike multiple-time programmable memories.

Innovation Solution

A method and integrated circuit design that includes a memory control circuit attempting to write data into a first register, verifying its correctness, and if unsuccessful, attempting to write it into a second register, utilizing a verification code and electrical measurements to ensure accurate data storage, with a chip configuration featuring write-protected and write-enabled memory cells within a single memory array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If OTP memory allows only single programming instance, then cost is reduced, but versatility and reliability are worsened

Engineering Contradiction:
ImprovecostVSAvoidprogramming flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The memory array is divided into multiple independent blocks (first block, second block, etc.), each capable of storing data independently. This segmentation allows the system to attempt programming in one block and fallback to another block if programming fails, thereby providing versatility while maintaining the cost benefits of OTP memory structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary verification of programming success immediately after each programming attempt. If the verification fails, the system proactively attempts programming in a different block before finalizing the configuration. This preliminary action prevents costly rework and ensures reliability while maintaining cost-effectiveness.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If OTP memory allows only single programming instance, then cost is reduced, but data integrity is worsened

Engineering Contradiction:
ImprovecostVSAvoiddata integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The system implements a feedback mechanism where each programming attempt is immediately verified by attempting to read back the programmed data. If the read-back does not match the expected data, the system receives feedback that programming failed and automatically attempts programming in a different block. This feedback loop ensures data integrity while maintaining cost benefits.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system prepares multiple programming blocks in advance as backup options. If the first programming attempt fails, previously prepared alternative blocks are ready for immediate use, cushioning against potential failures and ensuring data integrity without requiring expensive retry capabilities.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Adaptability or versatility

If multiple programming attempts are allowed in OTP memory, then versatility is improved, but device complexity is worsened

Engineering Contradiction:
Improveprogramming flexibilityVSAvoidmemory control circuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory is segmented into multiple independent blocks that can be programmed independently. The control logic simply attempts to program block 1, verifies success, and if failed, programs block 2. This segmentation approach provides versatility through multiple programming opportunities without requiring complex control circuits, as each block operates independently with simple sequential control.

Inventive Principle:
Principle #1Segmentation

4Reliability

If verification and multiple attempt mechanisms are implemented, then data integrity is improved, but manufacturing complexity is worsened

Engineering Contradiction:
Improvedata integrityVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory blocks perform self-verification by attempting to read back programmed data and comparing it with expected values. This self-service approach improves data integrity without requiring complex external verification circuits, as each block autonomously determines whether programming succeeded and triggers appropriate fallback actions.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables flexible and cost-effective programming of electronic devices by allowing data to be written into OTP memories with multiple attempts, ensuring data integrity and reducing production costs compared to multiple-time programmable memories.

Implementation Method 1

verifying whether the data has been correctly written in the at least one first register comprises measuring, for at least some of the memory cells of the at least one first register, an electrical value, and comparing each measured electrical value with at least one threshold

Methodology Applied
Scientific EffectElectrical measurement and threshold comparison: Electrical Resistance

Data Source

PatentUS11823750B2One-time programmable memory and method for verification and access
Publication Date: 2023.11.21 STMICROELECTRONICS SRL
  • US11823750B2 patent drawing
  • US11823750B2 patent drawing
  • US11823750B2 patent drawing

AI summary

A method for writing into a one-time programmable memory of an integrated circuit includes attempting, by a memory control circuit of the integrated circuit, to write data in at least one first register of the one-time programmable memory; verifying, by the memory control circuit, whether the data has been correctly written in the at least one first register; and, in case the data has not been correctly written in the at least one first register, attempting, by the memory control circuit, to write the data in at least one second register of the one-time programmable memory.