OTS Crossbar Memory Cells With Integrated Selector Switching
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Solution Overview
Problem
Conventional crossbar circuits require separate selector elements and transistors for access control, leading to increased complexity and cost in memory density and fabrication.
Innovation Solution
The integration of Ovonic threshold switching (OTS) memory devices as both selectors and memristors in crossbar arrays, utilizing chalcogenide materials with dielectric interface layers to enhance memory performance and eliminate the need for separate selector elements, allowing for a compact 1-memristor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate selector elements and transistors are used for access control in crossbar circuits, then reliability of memory access is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent merges the selector element and memory cell into a single integrated OTS memory device. The chalcogenide switching layer serves dual functions: as the memory storage element and as the selector switch. This eliminates the need for separate selector elements and transistors, reducing circuit structure complexity while maintaining access control reliability through the inherent switching characteristics of the OTS material.
Solution Approach 2:
The OTS memory device performs multiple functions simultaneously: it acts as both the memory cell for data storage and the selector element for access control. The chalcogenide switching layer can switch between conductive and insulating states to both store information and control current flow, making the device universal and eliminating the need for separate dedicated components.
2Ease of operation
If separate selector elements and transistors are used for access control, then ease of operation is improved, but manufacturing cost and fabrication complexity increase
Solution Approach 1:
By combining the selector and memory cell functions into a single OTS device, the patent reduces the number of fabrication steps and materials required. The integrated structure eliminates the need for separate transistor and selector element fabrication processes, thereby reducing manufacturing cost and fabrication complexity while preserving operational ease through the device's inherent switching capability.
3Device complexity
If OTS memory devices function as both selectors and memory cells, then device complexity is reduced, but leakage current may increase
Solution Approach 1:
The patent utilizes parameter changes in the chalcogenide switching layer's resistance state to achieve both switching and storage functions. By controlling the resistance of the chalcogenide layer through voltage application, the device can transition between high-resistance (off) and low-resistance (on) states, enabling it to function as both selector and memory cell while maintaining acceptable leakage current characteristics through proper parameter control.
4Ease of manufacture
If OTS memory devices function as both selectors and memory cells, then fabrication cost is reduced, but retention of memory states may be compromised
Solution Approach 1:
The patent maintains memory state retention by utilizing the stable resistance states of the chalcogenide switching layer. The OTS material can maintain its conductive or insulating state without continuous power supply, providing non-volatile memory retention. This parameter-based storage mechanism ensures that memory states are retained reliably while the same structure serves as both selector and memory cell, reducing fabrication cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density crossbar arrays with reduced fabrication and operation costs by utilizing OTS memory devices that function as both switches and memory cells, without the need for additional selector elements, while maintaining low leakage current and high retention of memory states.
Implementation Method 1
Crossbar circuits utilizing ovonic threshold switching (OTS) memory devices
Implementation Method 2
The first interface layer includes a first dielectric material that does not react with the chalcogenide and the first electrode
Data Source
AI summary
The present disclosure provides memory devices exhibiting Ovonic threshold switching (OTS) switching characteristics and crossbar circuits incorporating the memory devices. In some embodiments, an OTS memory device may include a first electrode, a first interface layer fabricated on the first electrode, a chalcogenide switching layer fabricated on the first interface layer, a second interface layer, and a second electrode. The chalcogenide switching layer comprises a chalcogenide. The first interface layer and the second interface layer may include a dielectric material that does not react with the chalcogenide and the electrode materials in the first electrode and the second electrode. The OTS memory device may function as both a switch and a non-volatile memory cell.