Outer Product Multiplier With Computation Gating and Circular Rotation
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Solution Overview
Problem
Existing digital hardware systems face inefficiencies in performing low-level matrix-matrix and matrix-vector mathematical operations in terms of performance and power consumption, particularly in implementing outer product matrix computations.
Innovation Solution
The development of an outer product multiplier (OPM) system that includes a hierarchical multiplication array logic (HMA) to perform simultaneous M×N outer product matrix computations, with computation gating and circular column rotation to optimize execution and data routing, utilizing A-multiplier-matrix, B-multiplicand-matrix, and C-product-matrix registers, and external data memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional digital hardware systems perform matrix-matrix and matrix-vector operations, then basic computational functionality is achieved, but performance and power consumption are inefficient
Solution Approach 1:
The system segments the matrix operation into distinct functional components: A-multiplier-matrix register, B-multiplicand-matrix register, C-product-matrix register, and hierarchical multiplication array logic. This segmentation allows each component to be optimized independently for both performance and power efficiency, enabling selective activation of computational units based on operation requirements.
Solution Approach 2:
The system implements dynamic computation gating through the computation decision matrix register, which selectively enables or disables specific multiplication operations based on the actual computational needs. This dynamic control prevents unnecessary computations and associated power consumption while maintaining high performance for required operations.
2Productivity
If simultaneous M×N outer product matrix computation is performed, then computational efficiency is improved, but computation complexity increases
Solution Approach 1:
The system transforms the traditional sequential matrix multiplication approach into a simultaneous M×N outer product computation by organizing the hierarchical multiplication array logic to process multiple product elements in parallel. This dimensional expansion from sequential to parallel processing achieves high computational efficiency while the structured organization of registers and logic gates manages the inherent complexity.
Solution Approach 2:
The hierarchical multiplication array logic is designed as a universal computing unit that can perform various matrix operations (matrix-matrix multiplication, matrix-vector multiplication, outer product computations) through a single unified structure. This multi-functionality reduces the need for separate specialized hardware for different operations, managing complexity while maintaining versatility.
3Loss of energy
If computation gating is applied to minimize unnecessary computations, then power consumption is reduced, but control complexity increases
Solution Approach 1:
The computation decision matrix register serves as an intermediary control structure that manages the gating of multiplication operations. Instead of complex control logic scattered throughout the system, this centralized intermediary structure selectively enables computation paths based on the actual data requirements, reducing power consumption while keeping control logic organized and manageable.
4Productivity
If circular column rotation is implemented to optimize data routing, then data movement efficiency is improved, but routing complexity increases
Solution Approach 1:
The system implements preliminary data reorganization through circular column rotation before the main multiplication computation. By pre-arranging data in the optimal configuration using the circular column rotation logic, the subsequent multiplication operations can proceed efficiently without requiring complex real-time routing adjustments during computation.
Data Source
AI summary
An outer product multiplier (GPM) system/method that integrates compute gating and input/output circular column rotation functions to balance time spent in compute and data transfer operations while limiting overall dynamic power dissipation is disclosed. Matrix compute gating (MCG) based on a computation decision matrix (CDM) limits the number of computations required on a per cycle basis to reduce overall matrix compute cycle power dissipation. A circular column rotation vector (CRV) automates input/output data formatting to reduce the number of data transfer operations required to achieve a given matrix computation result. Matrix function operators (MFO) utilizing these features are disclosed and include: matrix-matrix multiplication; matrix-matrix and vector-vector point-wise multiplication, addition, and assignment; matrix-vector multiplication; vector-vector inner product; matrix transpose; matrix row permute; and vector-column permute.