Semiconductor Output Circuit Layout for Dynamic ODT Timing
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Solution Overview
Problem
In semiconductor devices with ODT (On Die Termination) function, dynamic impedance changes to prevent signal reflection during high data transfer rates lead to increased circuit stages, causing inherent delay and timing deviations, especially when driver circuits for data output and ODT are shared.
Innovation Solution
An output circuit with a counter circuit generating an ODT control signal, a synchronizing circuit, a first selecting circuit activating ODT selection signals, and a second selecting circuit selecting driver circuits based on these signals, reducing the number of circuit stages between the synchronizing circuit and the data terminal by sharing driver circuits and strategically placing selecting circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ODT impedance is dynamically changed to prevent signal reflection during high data transfer rates, then the signal quality is improved, but the number of circuit stages between the synchronizing circuit and the data input-output terminal increases
Solution Approach 1:
The selecting circuit is divided into a first selecting circuit and a second selecting circuit. The first selecting circuit selects between different ODT impedance values, while the second selecting circuit selects which driver circuit to activate. This segmentation allows dynamic ODT impedance change without adding excessive circuit stages to the critical signal path.
Solution Approach 2:
The ODT control signal is generated in advance by the counter circuit based on timing information, and the first selecting circuit prepares the appropriate ODT selection signal before the data output operation. This preliminary action ensures that the ODT impedance is already set correctly when the data transmission occurs, avoiding additional delay during the actual data output.
2Adaptability or versatility
If the number of circuit stages between the synchronizing circuit and the data input-output terminal increases, then the ODT function can be dynamically changed, but the inherent delay of the DLL increases
Solution Approach 1:
The ODT impedance selection function is extracted from the main data output path and placed in a separate first selecting circuit that operates in parallel. This allows the ODT impedance to be selected without adding delay to the critical data transmission path, as the ODT control signal is generated independently by the counter circuit.
Solution Approach 2:
The driver circuit is designed to serve multiple functions: it can operate as a data output driver during read operations and as an ODT driver during write operations. This multi-functionality eliminates the need for separate dedicated ODT driver circuits, thereby reducing the overall number of circuit stages.
3Adaptability or versatility
If the number of circuit stages in the ODT path becomes larger than in the read path, then the ODT function can be implemented, but the data output timing or ODT execution timing deviates
Solution Approach 1:
The circuit configuration dynamically adapts to different operational modes. During read operations, the data output path is activated with its specific number of circuit stages. During write operations, the ODT path is activated with a matched number of circuit stages. The counter circuit and selecting circuits work together to ensure that the timing characteristics are maintained across different operational modes.
4Quantity of substance
If driver circuits for data output and ODT are shared, then the number of parts is decreased, but the number of circuit stages between the synchronizing circuit and the data input-output terminal further increases
Solution Approach 1:
The driver circuit is designed as a unified structure that can function both as a data output driver and as an ODT driver. The same physical driver circuit is controlled by different selection signals to perform different functions. This merging reduces the total number of driver circuits needed while the strategic placement of selecting circuits minimizes the impact on the number of circuit stages in the critical path.
Data Source
AI summary
An output circuit includes a counter circuit that generates an ODT control signal ODTa, plural driver circuits having the ODT function, a synchronizing circuit that synchronizes a signal transmitted from the counter circuit to the driver circuit with an internal clock DLL, a first selecting circuit that activates one of plural ODT selection signals ODTb and ODTc based on the ODT control signal ODTa, and a second selecting circuit that selects a driver circuit to be used out of the plural driver circuits based on the activated ODT selection signal. The first selecting circuit is provided between the counter circuit and the synchronizing circuit, and the second selecting circuit is provided between the synchronizing circuit and the driver circuit.