Output Control Circuit Using Divided Clock for Precise Read Timing
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Solution Overview
Problem
Semiconductor memory apparatuses face challenges in synchronizing external and internal clock signals accurately, leading to delays and difficulties in generating control signals at precise timing for data output, particularly due to the short period of internal clocks.
Innovation Solution
An output control circuit and output driving circuit are designed to include a period setting signal generation unit, clock division unit, shift unit, and output unit, which generate and process setup signals to produce an output enable reset signal synchronized with a divided clock, ensuring accurate timing for data output by securing the operating margin and precision in cycle and timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the internal clock period is shortened to increase operating speed, then productivity is improved, but measurement precision and timing accuracy deteriorate
Solution Approach 1:
A divided clock signal is introduced as an intermediary between the internal clock and the setup signal processing. The divided clock has a longer period than the internal clock, providing sufficient time margin for accurate setup signal timing while maintaining synchronization with the high-speed internal clock. This mediator resolves the conflict between fast operating speed and precise timing measurement.
2Loss of time
If the internal clock frequency is increased to reduce delay time, then loss of time is reduced, but reliability of signal synchronization deteriorates
Solution Approach 1:
The setup signal is generated and processed in advance using the divided clock before the actual data output operation. By preparing the setup signal timing using the longer-period divided clock, the system ensures proper synchronization is established beforehand, allowing the high-frequency internal clock to operate without compromising synchronization reliability.
3Ease of operation
If the cycle of the divided clock is made longer than the internal clock cycle, then ease of operation for signal processing is improved, but device complexity increases
Solution Approach 1:
The clock signal is segmented into two distinct signals: the original high-frequency internal clock for core operations and a divided clock with longer period for setup signal processing. This segmentation allows each clock to be optimized for its specific function, making signal processing easier while containing complexity through functional separation rather than complicating the entire clock system.
Data Source
AI summary
An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.