Overlapping Semiconductor Dice Package for Buck Converter Efficiency
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Solution Overview
Problem
The distributed two-stage power-conversion topology in buck converters suffers from lower overall power-conversion efficiency due to parasitic capacitances and inductances in interconnect wires, and the size difference between high-side and low-side power devices leads to inefficient heat dissipation and switching losses.
Innovation Solution
A semiconductor die package design that overlaps high-side and low-side devices with a lead frame to reduce parasitic capacitances and inductances, allowing for higher switching frequencies and improved power-conversion efficiency, while maintaining compactness and efficient heat dissipation through strategic placement and interconnection of dice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distributed two-stage power-conversion topology is used, then power-factor-correction performance is improved, but parasitic capacitances and inductances in interconnect wires increase causing lower power-conversion efficiency
Solution Approach 1:
The patent merges the high-side and low-side power devices into a single semiconductor die package with overlapping dice arrangement. This integration eliminates separate interconnect wires between devices, thereby reducing parasitic capacitances and inductances while maintaining the distributed two-stage power-conversion topology's PFC performance.
Solution Approach 2:
The patent employs a nested structure where one semiconductor die is disposed within a recessed area of another semiconductor die in the overlapping arrangement. This nesting approach minimizes the physical footprint and reduces the length of interconnect paths, thereby reducing parasitic effects and improving power-conversion efficiency.
2Ease of operation
If high-side and low-side power devices are separated, then device functionality is maintained, but parasitic capacitances and inductances increase leading to higher switching losses
Solution Approach 1:
The patent combines high-side and low-side power devices into a single integrated package with overlapping dice, reducing the physical separation between them. This integration shortens interconnect paths and reduces parasitic capacitances and inductances, thereby reducing switching losses while maintaining both devices' full functionality.
3Area of stationary object
If multiple semiconductor devices are placed in single package, then board space is reduced, but heat dissipation burden increases
Solution Approach 1:
The patent transitions from a planar side-by-side arrangement to a three-dimensional overlapping arrangement of semiconductor dice. This vertical integration reduces the lateral footprint on the circuit board while distributing heat generation across different vertical levels, allowing for more efficient heat management through the lead frame structure.
4Loss of energy
If overlapping dice arrangement is used, then parasitic capacitances and inductances are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent uses a nested arrangement where one die is placed within a recessed area of another die, creating a compact overlapping structure. This approach minimizes the need for complex external interconnect structures and simplifies the overall packaging process while achieving reduced parasitic capacitances and inductances.
Data Source
AI summary
Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed over a first portion of the leadframe, and the second die is disposed over a second portion of the leadframe with its recess portion overlying at least a portion of the first die. Another exemplary die package comprises a leadframe with a recessed area, a first semiconductor die disposed in the recessed area, and a second semiconductor die overlying at least a portion of the first die. Preferably, electrically conductive regions of both dice are electrically coupled to a conductive region of the leadframe to provide an interconnection between dice that has very low parasitic capacitance and inductance.