Overlapping Sub-Via Structure for High-Aspect-Ratio Via Filling
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Solution Overview
Problem
Current electronic devices face challenges in manufacturing vias with high aspect ratios, leading to difficulties in disposing conductive materials and potential wire breakage due to the large aspect ratio of the via.
Innovation Solution
The solution involves creating an electronic device with a substrate comprising two base layers, each with sub vias that overlap to form a via, where the sub vias have controlled pore sizes and overlapping widths, and are bonded with a buffer layer to reduce the aspect ratio and enhance conductive material placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the aspect ratio of the via is increased to achieve higher integration density, then the electrical connection efficiency is improved, but the conductive material cannot be easily disposed in the via leading to wire breakage
Solution Approach 1:
The via is segmented into multiple sub vias formed in separate base layers that are subsequently bonded together. This segmentation allows each sub via to have a manageable aspect ratio while the combined structure achieves the desired high aspect ratio for high-density integration, thereby resolving the contradiction between connection efficiency and manufacturing ease.
Solution Approach 2:
Multiple base layers with sub vias are nested and bonded together to form the final via structure. Each base layer contains sub vias that are positioned to overlap with corresponding sub vias in adjacent layers, creating a nested configuration that enables high aspect ratio vias while maintaining manufacturability of individual components.
2Device complexity
If the via aspect ratio is increased to reduce via count and improve integration density, then the device complexity is reduced, but the conductive material placement becomes difficult causing wire breakage
Solution Approach 1:
The via structure is divided into multiple sub vias across separate base layers, allowing each sub via to be manufactured with controlled dimensions and acceptable aspect ratio. This segmentation reduces the overall via count needed in the final device while maintaining manufacturing precision for each individual sub via.
Solution Approach 2:
The aspect ratio parameter of individual sub vias is controlled to be within manufacturable ranges, while the cumulative effect of multiple bonded layers achieves the high aspect ratio needed for reduced via count. This parameter management resolves the contradiction between device complexity and manufacturing precision.
3Ease of manufacture
If sub vias with small pore size are used to reduce aspect ratio, then the conductive material placement is easier, but the overlapping width control becomes critical to maintain via alignment
Solution Approach 1:
The pore size of sub vias is optimized to balance two competing requirements: small enough to reduce the aspect ratio of individual base layers for easier conductive material placement, but large enough to provide tolerance for overlapping width variations. This parameter optimization resolves the contradiction between manufacturing ease and alignment precision.
Solution Approach 2:
Different regions of the via structure have different quality requirements. The sub vias in each base layer are designed with specific pore sizes optimized for that layer's thickness, while the overlapping regions are designed with appropriate width margins. This localized quality control enables both easy material placement and reliable alignment.
Data Source
AI summary
An electronic device and a manufacturing method thereof are provided. The electronic device includes a substrate and a first buffer layer. The substrate has a via. The substrate includes a first base layer and a second base layer. The first base layer includes a first sub via penetrating the first base layer. The second base layer is bonded to the first base layer. The second base layer includes a second sub via penetrating the second base layer. The first sub via and the second sub via overlap each other to define the via. The first buffer layer is disposed in the via. The first sub via has a pore size, the first sub via and the second sub via have an overlapping region, the overlapping region has an overlapping width, and a difference between the pore size and the overlapping width ranges from 0.01 micrometers to 5 micrometers.