Overlapping Test Substrates for Semiconductor Chip Testing
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Solution Overview
Problem
Existing methods for testing semiconductor chips, such as using BOST or BIST circuits, face challenges in efficiently performing a wide variety of tests due to the large number of circuits required and space constraints, leading to difficulties in loading and operating these circuits effectively on print substrates or within semiconductor chips.
Innovation Solution
A test system comprising multiple test substrates arranged in overlapping layers, each with predetermined test circuits and connecting sections that transmit signals to chips under test, controlled by a central apparatus, allowing for parallel testing and efficient signal transmission, thereby enabling a range of tests including DC, analog, and function testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If BOST circuits are loaded on the probe card to test semiconductor chips, then the testing capability is improved, but the device complexity increases and it becomes difficult to load the circuits on the print substrate
Solution Approach 1:
The patent divides the testing system into separate functional modules: the probe card contains only simple electrical connection structures (probe pins), while the BOST circuits are implemented as separate test chips that can be selectively attached. This segmentation allows the probe card to remain simple for manufacturing while enabling complex testing capabilities through the modular test chips.
Solution Approach 2:
The patent introduces test chips as intermediary components between the simple probe card and the semiconductor chips being tested. These test chips contain the BOST circuits and serve as a mediator that bridges the gap between the simple probe card structure and the complex testing requirements, allowing flexible configuration of test circuits without complicating the probe card itself.
2Adaptability or versatility
If BIST circuits are provided in the semiconductor chips to enable testing, then the testing functionality is improved, but the space for circuits used for actual operation is decreased
Solution Approach 1:
The patent separates the testing functionality from the semiconductor chip by implementing BOST circuits in external test chips rather than integrating them into the chip under test. This segmentation allows the semiconductor chip to dedicate its entire area to operational circuits while the testing functions are performed by separate, attachable test chips connected through probe pins.
3Adaptability or versatility
If a wide variety of tests (DC, function, analog) are performed using BOST circuits on the print substrate, then the testing versatility is improved, but the device complexity and space requirements increase
Solution Approach 1:
The patent implements a dynamic reconfigurable testing system where test chips with different circuit configurations can be selectively attached to the probe card depending on the specific test requirements. This allows the system to adapt its complexity and configuration dynamically - using simple probe cards for basic tests and adding complex test chips only when needed for advanced DC, function, or analog testing.
Solution Approach 2:
The probe card is designed as a universal platform that can support multiple types of tests through the attachment of different test chips. The same probe card structure can accommodate various test configurations, making the system multi-functional without requiring separate probe cards for each test type, thereby managing complexity while maintaining versatility.
Data Source
AI summary
A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon.