Overlapping Word Line Memory for High-Speed Low-Power Access
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Solution Overview
Problem
Existing memory devices face challenges in achieving high access speed and low power consumption, particularly in microcontrollers with flash memory, where misaligned data access requires complex control and increased operating current.
Innovation Solution
A memory device configuration where consecutive addresses are accessed in parallel using overlapping word lines and bit lines, allowing dual assignment of memory cells to the same address, enabling single-access read operations and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory is divided into multiple memories for parallel access, then access speed is improved, but device complexity increases due to address conversion units and allocation control
Solution Approach 1:
The memory address space is segmented into multiple banks (first bank, second bank, third bank, fourth bank) that can be accessed in parallel. Each bank is associated with specific bit lines (BL0-BL3 for first bank, BL4-BL7 for second bank, etc.), allowing simultaneous access to different memory regions without requiring complex address conversion units.
Solution Approach 2:
The patent introduces a bank dimension to the memory architecture, organizing memory cells into multiple banks that can be independently accessed. This dimensional organization allows parallel access to misaligned data by selecting appropriate banks based on address bits, eliminating the need for complex address conversion while maintaining high access speed.
2Device complexity
If misaligned data is accessed using conventional memory structures, then device complexity is reduced, but access speed decreases due to multiple access operations required
Solution Approach 1:
The memory architecture dynamically selects which bank to access based on the address bits provided. The bit line selection is dynamic, allowing the system to adapt to different access patterns (aligned or misaligned) without requiring complex control logic. This dynamic selection enables misaligned data access in a single operation while keeping the device structure relatively simple.
Solution Approach 2:
The memory banks are designed to handle both aligned and misaligned access patterns universally. The same bank structure and bit line configuration can serve multiple access scenarios, eliminating the need for separate handling mechanisms for different access types and maintaining simplicity while achieving high-speed misaligned access.
3Speed
If two-word data is read by single memory access to improve speed, then access speed is improved, but power consumption increases due to doubled operating current
Solution Approach 1:
The patent activates only the specific banks and bit lines needed for the current access operation rather than activating all memory resources. When accessing misaligned data, only the relevant banks (e.g., first bank and second bank) are activated, reducing the overall power consumption compared to activating entire memory arrays, while still achieving high-speed access to the required data.
Solution Approach 2:
Different banks are activated based on the local requirements of the access operation. The memory system applies local quality by enabling specific bit lines and banks only when needed, rather than uniformly activating all memory resources. This localized activation reduces power consumption while maintaining high-speed access capability where needed.
Data Source
AI summary
A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.