Overlay Mark Grating Layout for IC Via Alignment Accuracy
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Solution Overview
Problem
As transistor features and metal interconnect structures decrease in size, alignment tolerances decrease, leading to misalignment of conductive vias and metal layers, resulting in nonfunctioning integrated circuits.
Innovation Solution
An enhanced overlay mark region with periodic structures and gratings is used for diffraction-based scatterometry alignment, ensuring proper alignment of subsequent mask features by maintaining a sufficient height of metal structures post-CMP process through the inclusion of a grating of first metal structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor features and metal interconnect structures decrease in size to increase computing power, then the number of transistors per area increases, but alignment tolerances decrease leading to misalignment of conductive vias and metal layers
Solution Approach 1:
The patent applies preliminary action by forming a grating of first metal structures (source/drain contact material) in advance before the CMP process. This pre-formed grating serves as a height reference that ensures the second metal structures (conductive via material) maintain sufficient height after CMP, enabling accurate overlay measurements and proper alignment of subsequent metal lines with conductive vias.
2Manufacturing precision
If alignment tolerances are reduced to improve manufacturing precision, then better alignment is achieved, but the complexity of the fabrication process increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a grating of first metal structures as a mediator between the CMP process and the overlay measurement. This intermediate grating structure provides a reference height that simplifies the overlay measurement process and ensures accurate alignment without requiring complex process controls.
3Shape
If the height of metal structures is reduced during CMP process, then planarization is achieved, but the signal strength for diffraction-based overlay measurements decreases
Solution Approach 1:
The patent applies preliminary action by forming the grating of first metal structures before the CMP process. This ensures that after CMP planarization, the second metal structures maintain sufficient height for strong overlay measurement signals, while the first metal grating remains as a reference structure to guide the alignment process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves alignment accuracy, enhances wafer yield, and ensures reliable contact between metal lines and conductive vias, resulting in better functioning integrated circuits.
Implementation Method 1
An enhanced overlay mark region with periodic structures and gratings is used for diffraction-based scatterometry alignment
Data Source
AI summary
An integrated circuit includes a device region and an overlay mark region. The device region includes a plurality of stacked channels of a transistor, a source/drain region of the transistor, a source/drain contact of a first material on the source/drain region, and a conductive via of a second material in contact with the source/drain contact. The overlay mark region includes a first diffraction grating of first metal structures of the first material and a first diffraction grating of second metal structures above of the second material above and offset from the first metal structures.