Oversampled Clock Recovery for Large Frequency Offset Locking
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Solution Overview
Problem
Conventional clock data recovery (CDR) circuits face challenges in locking data due to significant frequency differences between clock sources or low-frequency power/ground noise, limiting the ability to track frequency variations and maintain stable data recovery.
Innovation Solution
A clock-signal adjusting method and device that employs a Phase Lock Loop (PLL) circuit with a phase/frequency detector, data frequency detector, and phase detector to adjust the clock signal frequency and phase by sampling input data at multiple times the clock frequency, determining frequency relationships through data transition waveform shifts, and generating adjusting signals to synchronize the clock signal with the input data and reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase detector is used to track frequency variation, then phase locking can be achieved, but the ability to track significant frequency differences is limited
Solution Approach 1:
The patent segments the frequency detection function into two distinct detectors: a phase detector for precise phase tracking and a data frequency detector for detecting significant frequency differences. This segmentation allows each detector to specialize in its respective function, resolving the contradiction between precision and adaptability.
Solution Approach 2:
The data frequency detector acts as an intermediary that detects frequency differences and generates adjusting signals to pre-adjust the clock signal frequency before phase detection. This intermediary mechanism enables the system to handle significant frequency differences while maintaining precise phase locking capability.
2Speed
If PLL response is accelerated to solve minor data-locking problems, then locking speed improves, but significant frequency differences still cannot be effectively handled
Solution Approach 1:
The system performs preliminary frequency adjustment through the data frequency detector before phase detection and locking. By detecting frequency differences in advance and pre-adjusting the clock signal, the system prepares the PLL for faster and more reliable locking, addressing both speed and reliability requirements.
Solution Approach 2:
The patent implements a feedback mechanism where the data frequency detector continuously monitors frequency differences and adjusts the clock signal accordingly. This feedback loop ensures that both minor and significant frequency differences are corrected, maintaining reliable data locking while enabling fast response through the dual-detector architecture.
3Device complexity
If single frequency detection method is used, then device complexity is low, but ability to handle both phase and frequency adjustments is insufficient
Solution Approach 1:
The patent creates a universal clock adjustment system that can handle both phase adjustments (through the phase detector) and frequency adjustments (through the data frequency detector) within a single integrated architecture. This multi-functional design increases adaptability while maintaining reasonable complexity through modular organization.
Data Source
AI summary
A clock-signal adjusting method and device is used for adjusting a frequency of a clock signal according to a frequency of an input data. The input data is sampled with a sampling frequency m times of the clock frequency to obtain a data transition waveform indicating data transition timing distribution. A unitary bit time of the input data is divided into m zones. A frequency relationship between the clock signal and the input data is determined according to a shift of the data transition waveform relative to the zones. The frequency of the clock signal is adjusted according to the frequency relationship.