Oversampled Digital PLL Circuit Without Divider Noise Multiplication
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Solution Overview
Problem
Conventional digital phase-lock loop (PLL) circuits face challenges with noise multiplication due to the frequency divider in the feedback path, leading to reduced accuracy in phase lock and increased noise, particularly from phase detector/charge-pump and frequency divider sources.
Innovation Solution
The implementation of an oversampled digital PLL that eliminates the frequency divider by using a sampling phase detector and a digital controlled oscillator, incorporating a 1-bit quantizer for phase detection and noise-shaping, which spreads quantization noise across a wider frequency range, thereby suppressing inband noise and phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency divider is used in the feedback path of a conventional digital PLL, then the circuit can achieve frequency division and basic phase locking, but noise multiplication occurs leading to reduced phase lock accuracy and increased phase noise
Solution Approach 1:
The patent removes the frequency divider from the feedback path of the PLL circuit. By extracting this noise-generating component, the system eliminates the noise multiplication effect that occurs in conventional digital PLLs, thereby improving phase lock accuracy and reducing phase noise without sacrificing frequency division functionality through alternative means.
2Adaptability or versatility
If a conventional digital PLL architecture is used with frequency divider and phase detector/charge-pump, then frequency synthesis can be achieved, but noise from phase detector/charge-pump and frequency divider is multiplied and transferred to the output
Solution Approach 1:
The patent extracts and removes the frequency divider from the feedback path, eliminating the source of noise multiplication. This allows the system to maintain frequency synthesis capability through alternative architectures while preventing the multiplication and transfer of noise from phase detectors and other components to the output signal.
Solution Approach 2:
The patent transitions from a conventional charge-pump based phase detector to a digital-based phase detection mechanism. This substitution replaces the analog charge-pump circuitry with digital logic elements, thereby eliminating the noise generation and multiplication characteristics of the charge-pump while maintaining phase detection and frequency synthesis functionality.
3Measurement precision
If oversampling is implemented in the digital PLL, then loop bandwidth can be enhanced and inband noise suppressed, but the circuit complexity increases due to additional components like sampling phase detector and noise-shaping filters
Solution Approach 1:
The patent replaces complex analog loop filter circuits with digital noise-shaping filters and oversampling mechanisms. By transitioning to digital signal processing techniques, the system achieves enhanced loop bandwidth and inband noise suppression while the apparent complexity is managed through digital implementation rather than analog component proliferation.
Data Source
AI summary
In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.