Oversized Via Mask Alignment in Dual Damascene IC Manufacturing
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Solution Overview
Problem
During the manufacturing of ultra-high density integrated circuits, mask layer-to-mask layer overlay errors lead to misalignment of vias and metal lines, resulting in reduced pitch between circuit elements, which can cause shorts and dielectric breakdown, affecting the reliability and functionality of the ICs.
Innovation Solution
A method involving the formation of a stack with specific layers, including a dielectric layer, capped layer, hard mask layer, and photoresist layers, where oversized via masks are patterned to extend across opposing sides of metal line masks, allowing for alignment and etching operations that minimize pitch errors, ensuring accurate placement of vias relative to metal lines through a modified dual damascene process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dual damascene process with standard via masks is used, then manufacturing process is simple, but mask overlay errors cause via misalignment with metal lines, reducing pitch and causing shorts or dielectric breakdown
Solution Approach 1:
The patent applies preliminary action by forming via masks that intentionally extend beyond the metal line mask boundaries before etching. This pre-compensation for potential overlay errors ensures that even if alignment shifts occur during processing, the via openings will still fully cover the metal line features, preventing shorts and dielectric breakdown while maintaining manufacturing simplicity
Solution Approach 2:
The patent implements local quality by creating non-uniform via mask dimensions - the via masks extend beyond metal line masks only in critical areas where alignment errors could cause failures, while maintaining standard dimensions in non-critical areas. This localized extension provides targeted protection against overlay errors without unnecessarily increasing overall process complexity
2Manufacturing precision
If via masks are made oversized to extend across opposing sides of metal line masks, then via alignment accuracy improves to photolithography resolution limit, but chip area increases
Solution Approach 1:
The patent applies local quality by extending via masks only in specific directions (across opposing sides of metal line masks) where pitch control is most critical, rather than uniformly increasing mask size in all directions. This localized extension achieves the necessary manufacturing precision at the photolithography resolution limit while minimizing the increase in overall chip area
Solution Approach 2:
The patent uses partial action by making via masks oversized only to the extent necessary to compensate for expected overlay errors, rather than excessively large margins. The extension distance is carefully controlled to provide sufficient alignment tolerance while avoiding unnecessary area consumption that would reduce chip density
Data Source
AI summary
A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.