Oxide Bonding Layer Treatment for 3D Wafer Alignment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current bonding techniques for semiconductor wafers result in corner rounding, voids, and roughness of interconnect structures due to etching processes, affecting alignment and bonding energy during wafer-to-wafer and chip-to-chip connections.

Innovation Solution

A post-treatment process involving selective deposition and plasma activation of an oxide bonding layer on semiconductor wafers to enhance bonding energy, minimizing voids and misalignments by forming a channel between interconnect structures, followed by annealing to physically connect the wafers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If etching techniques are used to recess interconnect structures for alignment and expansion, then proper alignment and bonding are enabled, but corner rounding, voids, and roughness of interconnect structures occur

Engineering Contradiction:
Improvealignment precisionVSAvoidinterconnect structure integrity
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The patent applies preliminary action by forming a mandrel structure before the bonding process. The mandrel is deposited and patterned to define the interconnect structure geometry in advance, preventing corner rounding and void formation during subsequent bonding operations. This preparatory step ensures that interconnect structures maintain their intended shape while enabling proper alignment.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a mandrel as an intermediary structure that mediates between the bonding requirements and interconnect structure integrity. The mandrel serves as a temporary support and alignment reference during the bonding process, allowing interconnect structures to be formed without direct etching that would cause damage. After bonding, the mandrel is removed, leaving intact interconnect structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If bonding energy is increased to improve wafer alignment and bonding, then bonding strength is enhanced, but process complexity increases

Engineering Contradiction:
Improvebonding energyVSAvoidprocess complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by controlling the deposition conditions of the mandrel material to achieve optimal bonding energy. By adjusting deposition parameters such as temperature, pressure, and material composition during mandrel formation, the bonding interface achieves high bonding strength without requiring complex post-bonding processing steps.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method increases bonding energy and alignment efficiency, reducing voids and misalignments, and enhances the bonding process by forming a channel that expands interconnect structures for improved wafer connections.

Implementation Method 1

A selective deposition technique can be performed to deposit oxide materials over the top surface of the dielectric layers... The bonding energy can be enhanced based on the pretreatment of at least one of the wafers

Methodology Applied
Scientific EffectPlasma activation: Plasma

Implementation Method 2

The first and second substrates can be heated/annealed, thereby expanding and physically connecting the interconnect structures of the two wafers

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 3

A selective deposition technique can be performed to deposit oxide materials over the top surface of the dielectric layers

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS12577665B2Next generation bonding layer for 3D heterogeneous integration
Publication Date: 2026.03.17 TOKYO ELECTRON LTD
  • US12577665B2 patent drawing
  • US12577665B2 patent drawing
  • US12577665B2 patent drawing

AI summary

Devices and methods for forming semiconductor devices are disclosed. The semiconductor device can include a plurality of semiconductor wafers. The plurality of semiconductor wafers can have a dielectric bonding layer disposed thereupon. The dielectric bonding layers can be treated to increase a bonding energy with other semiconductor wafers. A wafer having a treatment applied to a bonding layer can be bonded to another wafer.