Oxide Channel Ferroelectric Transistor Structure for Interface Endurance
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving structural stability and operational reliability in reduced spaces, particularly in ferroelectric field effect transistors, where the endurance of signal information storage is compromised due to the formation of unwanted interfacial insulation layers and reduced transistor endurance.
Innovation Solution
A semiconductor device design incorporating first and second oxide channel layers with different band gap energies, a ferroelectric layer adjacent to these channels, and a gate electrode layer, where the ferroelectric layer is formed in a recessed space to prevent unwanted insulation layer formation, enhancing signal storage and transistor endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the space is reduced to increase memory cell density, then the area occupied by memory cells is reduced, but unwanted interfacial insulation layers form and transistor endurance deteriorates
Solution Approach 1:
The channel layer is segmented into multiple oxide semiconductor layers with different band gaps (first oxide channel layer with first band gap, second oxide channel layer with second band gap). This segmentation allows each layer to perform specific functions: the layer with larger band gap prevents interfacial insulation layer formation, while the layer with smaller band gap maintains good interface with the ferroelectric layer, thus resolving the contradiction between reduced area and maintained reliability.
Solution Approach 2:
The patent uses a composite structure of multiple oxide semiconductor layers with different band gap energies. This composite material approach combines the advantages of materials with large band gaps (resistance to interfacial insulation layer formation) and materials with small band gaps (good interface compatibility with ferroelectric layer), thereby maintaining transistor endurance in reduced space configurations.
2Device complexity
If a single oxide channel layer is used, then the device structure is simple, but unwanted interfacial insulation layers form at the interface with the ferroelectric layer
Solution Approach 1:
Different regions of the channel layer are assigned different material properties: the first oxide channel layer (with larger band gap) is positioned to face the gate electrode to prevent interfacial insulation layer formation, while the second oxide channel layer (with smaller band gap) is positioned to face the ferroelectric layer to ensure good interface compatibility. This local differentiation of material properties eliminates harmful interfacial effects without requiring complex overall structure.
3Stability of the object's composition
If the oxide channel layer has large band gap to prevent interfacial insulation layer formation, then interfacial stability is improved, but interface quality with ferroelectric layer deteriorates
Solution Approach 1:
The channel layer is divided into two segments with different band gap characteristics. The first oxide channel layer with larger band gap provides stability and prevents interfacial insulation layer formation at the gate electrode interface, while the second oxide channel layer with smaller band gap ensures good interface quality with the ferroelectric layer. This segmentation resolves the contradiction between stability and interface quality.
Solution Approach 2:
The patent changes the band gap parameter across different channel layers. By using oxide semiconductors with different band gap energies in different layers, the patent optimizes the interface properties: larger band gap for gate electrode interface stability and smaller band gap for ferroelectric layer interface quality, thereby resolving the contradiction between these two requirements.
Data Source
AI summary
A semiconductor device according to an embodiment includes a substrate, a source electrode layer and a drain electrode layer that are disposed over the substrate to be spaced apart from each other in a direction substantially perpendicular to a surface of the substrate, first and second oxide channel layers the extend in the direction substantially perpendicular to the surface of the substrate between the source electrode layer and the drain electrode layer, a ferroelectric layer disposed adjacent to the first and second oxide channel layers, and a gate electrode layer disposed on the ferroelectric layer. The first and second oxide channel layers have different band gap energies from each other.