Oxide-Semiconductor GAA Channel Structure for FinFET Scaling
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Solution Overview
Problem
As the scale of fin width in fin field effect transistors (FinFETs) decreases, channel width variations can lead to mobility loss, making it challenging to maintain high integration density and efficiency in semiconductor devices.
Innovation Solution
The use of gate-all-around (GAA) transistors with semiconductor oxide-based channel layers, such as indium gallium zinc oxide (IGZO), which provides improved electrostatic control and higher mobility, allowing for increased on-current and easier fabrication in three-dimensional integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin width is reduced to increase integration density, then more components can be integrated into a given area, but channel width variations lead to mobility loss
Solution Approach 1:
The patent transitions from planar FinFET architecture to three-dimensional gate-all-around (GAA) nanosheet architecture. The gate structure completely surrounds the channel in three dimensions, providing superior electrostatic control and eliminating mobility loss associated with reduced fin width. This dimensional change allows continued scaling while maintaining channel uniformity and carrier mobility.
Solution Approach 2:
The patent employs oxide-based semiconductor materials (such as IGZO - indium gallium zinc oxide) for the channel layers, combining the benefits of high electron mobility with compatibility with existing CMOS fabrication processes. This composite material approach enables high-performance transistors at scaled dimensions while maintaining manufacturing feasibility.
2Ease of manufacture
If conventional FinFET architecture is used, then fabrication process is well-established, but electrostatic control and mobility are limited
Solution Approach 1:
The gate structure completely surrounds the channel in three dimensions, providing superior electrostatic control and eliminating mobility loss associated with reduced fin width. This dimensional change allows continued scaling while maintaining channel uniformity and carrier mobility.
3Ease of manufacture
If high processing temperatures are used, then existing CMOS structures can be fabricated, but front-end structures are affected and multiple tiers cannot be integrated
Solution Approach 1:
The oxide-based semiconductor channel layers enable transistor fabrication at lower processing temperatures compared to conventional silicon-based channels. This parameter change in processing temperature allows the back-end-of-line (BEOL) transistors to be fabricated without affecting front-end-of-line (FEOL) CMOS structures, enabling monolithic 3D integration with multiple functional tiers.
Data Source
AI summary
A method includes forming a fin over a substrate, the fin comprising alternately stacking first oxide-based semiconductor layers and second oxide-based semiconductor layers, removing the second oxide-based semiconductor layers to form a plurality of spaces each between corresponding ones of the first oxide-based semiconductor layers, and depositing in sequence a gate dielectric layer and a gate metal into the plurality of spaces each between corresponding ones of the second oxide-based semiconductor layers.