Oxide Semiconductor Memory Channel Structure for Low Leakage
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Solution Overview
Problem
Current semiconductor memory devices face limitations in integration density and performance due to high equipment costs and poor interface characteristics between oxide semiconductor channel layers and conductive lines, leading to increased leakage current and reduced operational efficiency.
Innovation Solution
A semiconductor memory device is designed with a channel layer comprising sequentially stacked oxide semiconductor layers, where the first layer has higher crystallinity for improved carrier mobility and interface characteristics, and dielectric layers with varying dielectric constants to reduce leakage current and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a two-dimensional or planar semiconductor memory device is used, then the integration density is determined by the area occupied by a unit memory cell, but the integration density is limited due to the level of fine pattern formation technology and high equipment costs
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by forming vertical channel trenches that extend in the thickness direction of the substrate. This dimensional change allows the channel to extend vertically rather than horizontally, enabling higher integration density without being constrained by fine pattern formation technology limits.
Solution Approach 2:
The patent divides the vertical channel into multiple segments by forming first and second gate electrodes spaced apart in the first direction, creating multiple gate-controlled regions along the vertical channel. This segmentation allows for more complex memory cell operations while maintaining high integration density.
2Reliability
If oxide semiconductor channel layers are used, then carrier mobility can be improved, but interface characteristics between the oxide semiconductor channel layer and conductive line deteriorate, leading to increased leakage current
Solution Approach 1:
The patent forms a composite channel layer structure consisting of a first oxide semiconductor layer with high crystallinity and a second oxide semiconductor layer with lower crystallinity. This composite structure combines the high carrier mobility of crystalline oxide semiconductors with the good interface characteristics of less crystalline layers, reducing leakage current while maintaining mobility.
Solution Approach 2:
The patent applies different crystallinity qualities to different parts of the oxide semiconductor channel layer. The first oxide semiconductor layer has high crystallinity for improved carrier mobility, while the second oxide semiconductor layer has lower crystallinity for better interface characteristics with the conductive line, thereby reducing leakage current.
Data Source
AI summary
A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.