3D Oxide Semiconductor Memory Stack for Low-Power Data Retention
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving low power consumption, reduced size, and improved reliability in data retention and reading, particularly in memory devices utilizing oxide semiconductor transistors.
Innovation Solution
A semiconductor device is designed with a novel structure comprising a first element layer with a reading circuit, a second element layer with an amplifier circuit, and a third element layer with memory cells, where the second and third layers are stacked over the first, and the amplifier and memory cells are connected via bit lines. The device includes oxide semiconductor transistors with a capacitor in an opening portion and utilizes a back gate structure for enhanced control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional planar structure is used for memory devices, then the device area is large, but the memory capacity per unit area is limited
Solution Approach 1:
The patent transitions from a conventional planar (2D) memory structure to a three-dimensional stacked structure. Multiple memory cell layers are vertically stacked, with each layer containing memory cells, bit lines, and word lines. This vertical stacking enables significantly increased memory capacity per unit area by utilizing the third dimension (height) for additional storage layers, effectively multiplying the storage density without proportionally increasing the footprint area.
2Use of energy by moving object
If oxide semiconductor transistors are used for data retention, then power consumption is reduced, but reliability in high-temperature environments deteriorates
Solution Approach 1:
The patent modifies the physical and chemical parameters of the oxide semiconductor material to enhance its thermal stability. Specific compositional adjustments and structural optimizations are implemented in the oxide semiconductor layer to reduce oxygen vacancy formation and improve carrier mobility at elevated temperatures. These parameter changes enable the oxide semiconductor transistor to maintain low power consumption characteristics while achieving sufficient reliability for data retention in high-temperature operating environments.
3Area of stationary object
If multiple element layers are stacked to increase memory capacity, then the device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory device into multiple discrete element layers, where each layer contains specific functional components (memory cells, bit lines, word lines). This segmentation allows for modular manufacturing processes where each layer can be formed, patterned, and tested relatively independently before stacking. The segmented approach simplifies the overall manufacturing complexity by breaking down the complex three-dimensional structure into manageable sequential fabrication steps, rather than attempting to create the entire stacked structure in a single complex process.
Data Source
AI summary
A semiconductor device with a novel structure is provided. A first element layer provided with a reading circuit, a second element layer provided with an amplifier circuit, and a third element layer provided with a memory cell are included. The second element layer is stacked over the first element layer. The third element layer is stacked over the second element layer. The memory cell and the amplifier circuit are electrically connected to each other through a first bit line. The amplifier circuit and the reading circuit are electrically connected to each other through a second bit line. The amplifier circuit has a function of transmitting a signal corresponding to a potential of the first bit line to the second bit line. The amplifier circuit includes a first transistor in which a first semiconductor layer including a channel formation region includes an oxide semiconductor. The memory cell includes a second transistor in which a second semiconductor layer including a channel formation region includes an oxide semiconductor and a capacitor. The first semiconductor layer is provided in a direction parallel to a surface of a substrate provided with the first element layer. The second semiconductor layer is provided in a direction perpendicular to the surface of the substrate provided with the first element layer.