Oxide Semiconductor Device Structure for Channel Hydrogen Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The diffusion of hydrogen into the channel region of oxide semiconductor devices leads to a decrease in manufacturing yield and reliability due to changes in threshold voltage, necessitating a solution that supplies hydrogen to the source and drain regions while preventing its entry into the channel region.
Innovation Solution
A semiconductor device configuration with a hydrogen-trapping region is implemented, utilizing a nitride insulating layer with a sidewall matching the gate electrode pattern and insulating layers to trap hydrogen, thereby preventing its entry into the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an oxide layer containing excessive oxygen is used as an insulating layer to suppress hydrogen entry into the channel region, then hydrogen diffusion is suppressed, but the reliability of the semiconductor device is significantly reduced due to electron trapping
Solution Approach 1:
The insulating layer is divided into multiple distinct layers: a first insulating layer (oxide layer) that supplies hydrogen to source and drain regions, and a second insulating layer (nitride layer) that acts as a barrier to prevent hydrogen from entering the channel region. This segmentation allows each layer to perform its specific function without the harmful side effects of the other.
Solution Approach 2:
Different regions of the insulating structure are given different properties: the first insulating layer has high hydrogen supply capability (oxide characteristics) while the second insulating layer has high hydrogen barrier properties (nitride characteristics). This local differentiation of properties enables selective hydrogen management - allowing it where needed and blocking it where harmful.
2Quantity of substance
If hydrogen is supplied to source and drain regions to form low-resistance regions, then conductivity is improved, but hydrogen diffusion into the channel region causes threshold voltage variation and reduces manufacturing yield
Solution Approach 1:
The insulating layer is segmented into a first layer that facilitates hydrogen supply to source and drain regions and a second layer that prevents hydrogen from reaching the channel region. This segmentation enables precise control over hydrogen distribution, ensuring adequate hydrogen concentration in source/drain regions for low resistance while maintaining threshold voltage stability in the channel region.
Solution Approach 2:
The second insulating layer (nitride layer) acts as an intermediary barrier between the hydrogen-supplying first insulating layer and the channel region. It mediates hydrogen transport by allowing hydrogen to reach source and drain regions while blocking further diffusion into the channel region, thus controlling hydrogen distribution and preventing threshold voltage variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hydrogen-trapping region effectively suppresses hydrogen diffusion into the channel region, maintaining device reliability and improving manufacturing yield by stabilizing threshold voltage.
Implementation Method 1
the nitride insulating layer has a first sidewall having a shape matching a pattern of the gate electrode in a plan view, and the first sidewall is in contact with the insulating layer
Implementation Method 2
In the oxide semiconductor, carriers are generated when hydrogen bonds to oxygen defects. In the semiconductor device, this mechanism can be used to form a source region and a drain region, which are low-resistance regions, by forming oxygen defects in an oxide semiconductor layer and supplying hydrogen to the oxygen defects.
Data Source
AI summary
A semiconductor device according to an embodiment of the present invention includes: a first oxide insulating layer; an oxide semiconductor layer above the first oxide insulating layer; a second oxide insulating layer covering the oxide semiconductor layer; a nitride insulating layer above the second oxide insulating layer; a gate electrode above the nitride insulating layer; and an insulating layer covering the gate electrode, wherein the nitride insulating layer has a first sidewall having a shape matching a pattern of the gate electrode in a plan view, and the first sidewall is in contact with the insulating layer.