Oxide Semiconductor Memory Cell for Non-Volatile Data Retention
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Solution Overview
Problem
Conventional semiconductor storage devices face limitations in retaining data without power, requiring frequent refresh operations in volatile devices and suffering from write cycle limitations and high voltage needs in non-volatile devices, which affects reliability and speed.
Innovation Solution
A semiconductor storage device using a memory cell array with a decoder and control circuit, where data is stored by turning off a selection transistor with an oxide semiconductor channel region, eliminating the need for high voltage and allowing unlimited write cycles, and reducing leakage current to enhance data retention and operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a volatile storage device (DRAM) is used to achieve high-speed operation, then writing and reading data is fast, but the device requires frequent refresh operations and has short data retention time
Solution Approach 1:
The invention changes the material parameter of the transistor channel from conventional semiconductor to oxide semiconductor, which fundamentally alters the electrical characteristics to achieve both high-speed operation and long data retention without refresh operations
Solution Approach 2:
The invention uses a composite structure combining oxide semiconductor channel with conventional semiconductor components, leveraging the unique properties of oxide semiconductor to resolve the contradiction between speed and retention time
2Duration of action of stationary object
If a non-volatile storage device (flash memory) is used to achieve long data retention, then data is retained indefinitely, but the device has limited write cycles and requires high voltage
Solution Approach 1:
The invention changes the transistor material to oxide semiconductor, which fundamentally reduces leakage current and enables non-volatile operation without the tunneling current damage that limits flash memory write cycles
Solution Approach 2:
The invention extracts and eliminates the floating gate structure from flash memory, using only the oxide semiconductor transistor to achieve non-volatile storage, thereby removing the source of write cycle limitation while maintaining long retention
3Duration of action of stationary object
If flash memory is used to achieve non-volatile storage, then data is retained without power, but the device requires high voltage for writing and erasing operations
Solution Approach 1:
The invention changes the transistor material to oxide semiconductor, which enables non-volatile operation at low voltage by reducing leakage current without requiring high-voltage tunneling mechanisms
Solution Approach 2:
The invention removes the floating gate structure that requires high voltage for charge injection and extraction, achieving non-volatile storage through oxide semiconductor transistor leakage reduction alone at conventional low operating voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables long-term data retention without power, eliminates write cycle limitations, and reduces power consumption, while ensuring high-speed operations and improved reliability by using an oxide semiconductor with low off-state current.
Implementation Method 1
data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor
Data Source
Figure 1A~1B
Figure 2A~2H
Figure 3A~3C
AI summary
A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.