Oxide Semiconductor Memory Device Reducing Parasitic Resistance
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Solution Overview
Problem
Current DRAM memory devices face challenges in increasing memory capacity per unit area while maintaining data retention and reducing error incidence due to high parasitic resistances and capacitances in bit and word lines, leading to increased power consumption and operational errors.
Innovation Solution
The solution involves a memory device design with oxide semiconductor transistors and capacitors, where bit and word line driver circuits are stacked and connected through wirings with strategically placed connection points on the edges between memory cell arrays, reducing parasitic resistances and capacitances, and using amplifying elements to enhance signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the area of the capacitor is reduced to increase memory capacity per unit area, then the memory capacity per unit area is improved, but the capacitance value decreases resulting in smaller difference between charge amounts and shorter holding period
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional semiconductor to oxide semiconductor, which fundamentally alters the off-state current characteristic. This parameter change enables the transistor to maintain extremely low leakage current even when the capacitor area is reduced, thus preserving the holding period while achieving higher memory capacity per unit area.
2Quantity of substance
If the number of memory cells is increased to achieve large storage capacity, then the storage capacity is improved, but the parasitic capacitance and parasitic resistance of the bit line increase making it difficult to accurately read data
Solution Approach 1:
The patent changes the transistor material to oxide semiconductor, which dramatically reduces the off-state current. This parameter change allows for larger memory arrays to be constructed without the parasitic effects overwhelming the signal, as the lower leakage current maintains better signal integrity even with increased parasitic capacitance and resistance.
3Quantity of substance
If the number of memory cells is increased to achieve large storage capacity, then the storage capacity is improved, but the parasitic resistance of the word line increases causing signal delay and potential drop leading to operational errors
Solution Approach 1:
The patent changes the transistor material to oxide semiconductor, which fundamentally reduces the off-state current parameter. This enables larger memory arrays to be constructed where the reduced leakage current compensates for the increased parasitic resistance in word lines, maintaining signal integrity and operational reliability even with extended word line lengths.
4Ease of manufacture
If conventional semiconductor transistors are used in memory cells, then the structure is simple and manufacturing is easier, but the off-state current is high requiring frequent refresh operations and increasing power consumption
Solution Approach 1:
The patent changes the semiconductor material parameter from conventional silicon-based semiconductor to oxide semiconductor. This material parameter change fundamentally alters the electrical characteristics, producing extremely low off-state current that reduces refresh frequency requirements and power consumption, while still being compatible with existing thin-film fabrication processes.
Data Source
AI summary
A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.