Oxide Semiconductor Memory with Stacked Gate Structure
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Solution Overview
Problem
Current semiconductor memory devices fail to simultaneously achieve high speed, high storage density, and reduced bit cost, making them inadequate for the increasing data demands of information terminals and cloud services.
Innovation Solution
A semiconductor memory design incorporating an oxide semiconductor layer with a stacked gate structure, including conductive layers and transistors arranged in a specific configuration to optimize data storage and retrieval, allowing for high-speed data transfer and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory device structures are used, then manufacturing processes are simpler, but storage density and operational speed cannot simultaneously achieve high performance
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional stacked structures, where memory cells are arranged in multiple layers vertically. This dimensional change enables significantly higher storage density within the same footprint area while maintaining manufacturability through established semiconductor processing techniques adapted for 3D stacking.
Solution Approach 2:
The patent implements nested structures where conductive layers, insulating layers, and memory cell components are stacked and integrated within each other. Multiple memory cell layers are nested vertically, with shared bit lines and word lines, achieving high storage density through efficient spatial utilization without proportionally increasing device complexity.
2Quantity of substance
If higher storage density is achieved through increased capacity, then data demands are met, but bit cost increases
Solution Approach 1:
The patent designs memory structures where single bit lines and word lines serve multiple memory cell layers simultaneously. This multi-functionality increases data capacity without proportionally increasing the number of conductive interconnects, thereby reducing bit cost through efficient resource sharing across stacked memory layers.
Solution Approach 2:
The patent merges multiple memory cell layers into a single integrated three-dimensional structure with shared control lines and interconnects. This consolidation achieves increased data capacity while reducing the overall number of manufacturing steps and materials required compared to separate planar memory devices, thus lowering bit cost.
3Speed
If memory devices operate at high speed, then data transfer efficiency improves, but power consumption increases
Solution Approach 1:
The patent divides the memory device into multiple independent stacked layers, each capable of simultaneous operation. This segmentation enables parallel data access across layers, increasing overall data transfer speed while distributing power consumption across multiple smaller units, thereby improving energy efficiency compared to a single large planar memory device.
Data Source
AI summary
According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.