Multilayer Oxide Semiconductor Thin Film Transistor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Miniaturization of transistors leads to deterioration of electrical characteristics such as on-state current, off-state current, threshold voltage, and subthreshold swing value, due to increased short-channel effects and variations in channel width and length.
Innovation Solution
A semiconductor device structure with a multilayer oxide semiconductor film configuration, where a first oxide semiconductor film is thicker than the sum of a second and third oxide semiconductor film and gate insulating film, with the gate electrode covering the second oxide semiconductor film from the top and side surfaces, reducing interface scattering and enhancing carrier control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is decreased to miniaturize the transistor, then the integration degree increases, but the off-state current increases and electrical characteristics deteriorate due to short-channel effects
Solution Approach 1:
The patent applies surrounded channel structure where the gate electrode wraps around the channel region from top, bottom, and side surfaces, transitioning from conventional planar gate control to three-dimensional gate control. This dimensional change enhances electric field coverage and carrier control without requiring further channel length reduction, thus maintaining integration benefits while suppressing short-channel effects
Solution Approach 2:
The gate electrode is designed to surround the channel formation region, with the gate insulating film and gate electrode nested around the oxide semiconductor films from multiple directions. This nested structure provides comprehensive gate control over the channel, improving carrier mobility and electrical characteristics while maintaining miniaturized dimensions
2Productivity
If the channel width is decreased to miniaturize the transistor, then the integration degree increases, but the on-state current decreases
Solution Approach 1:
The surrounded channel structure extends gate control from the conventional top-surface-only configuration to include bottom and side surface coverage. This three-dimensional gate control compensates for the reduced channel width by enhancing electric field strength and carrier modulation efficiency, maintaining on-state current despite miniaturization
3Power
If the thickness of the semiconductor film is increased to increase on-state current, then the channel formation area increases, but carrier scattering at the interface increases and on-state current cannot be sufficiently increased
Solution Approach 1:
The semiconductor structure is segmented into multiple oxide semiconductor films with distinct functions: the first oxide semiconductor film provides a thick channel region for high on-state current, while the second and third oxide semiconductor films form interface layers that reduce carrier scattering. This segmentation allows simultaneous optimization of current carrying capacity and interface quality
Solution Approach 2:
The patent uses a composite structure of multiple oxide semiconductor films with different compositions and properties. The first oxide semiconductor film (In-Ga-Zn-O) provides high carrier mobility, while the second and third films provide interface protection and scattering reduction. This composite approach achieves high on-state current without excessive interface scattering
Data Source
AI summary
A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.