Oxide Semiconductor Thin Film Transistor Gate Segmentation

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Solution Overview

Problem

Conventional oxide semiconductor thin film transistors deteriorate and malfunction when a high voltage is continuously applied to their gate electrode, making them unsuitable for durable and reliable use in display devices.

Innovation Solution

The design includes a gate electrode with a larger area than the active layer, a gate insulation layer with a protrusion, and an etch stopper layer to reduce parasitic capacitance and enhance durability, using an oxide material with specific electron carrier concentrations for the active layer, and a passivation layer to protect the transistor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the gate electrode area is increased to improve voltage handling capability, then the transistor can withstand higher voltages, but the parasitic capacitance increases causing deterioration and malfunction

Engineering Contradiction:
Improvevoltage handling capabilityVSAvoidparasitic capacitance
Core Design Contradiction:
StrengthVSObject-generated harmful factors

Solution Approach 1:

The gate electrode is divided into two distinct parts: a first gate electrode with a first area and a second gate electrode with a second area smaller than the first area. This segmentation allows the larger first gate electrode to provide high voltage handling capability while the smaller second gate electrode region reduces parasitic capacitance, thereby resolving the contradiction between voltage strength and harmful capacitance effects.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the gate electrode are given different areas and functions. The first gate electrode region has a larger area optimized for voltage handling, while the second gate electrode region has a smaller area optimized for reducing parasitic capacitance. This local differentiation allows each region to excel at its specific function, resolving the overall contradiction.

Inventive Principle:
Principle #3Local quality

2Productivity

If continuous high voltage is applied to improve switching performance, then the transistor switching capability is enhanced, but the transistor deteriorates and malfunctions due to reduced durability

Engineering Contradiction:
Improveswitching performanceVSAvoiddurability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The segmented gate electrode structure with different area regions enables the transistor to maintain high switching performance through the larger first gate electrode area while the smaller second gate electrode area prevents deterioration by reducing parasitic capacitance, thus preserving durability under continuous high voltage operation.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the active layer area is increased to improve current conduction, then the transistor conductivity is enhanced, but the parasitic capacitance increases leading to malfunction

Engineering Contradiction:
ImproveconductivityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The active layer is configured with a specific area relationship to the gate electrode, where the active layer area is optimized to provide sufficient current conduction path while maintaining appropriate spacing and overlap characteristics that limit parasitic capacitance formation, thereby achieving both good conductivity and low parasitic effects.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8450733B2Oxide semiconductor thin film transistor, and method of manufacturing the same
Publication Date: 2013.05.28 SAMSUNG DISPLAY CO LTD
  • US8450733B2 patent drawing
  • US8450733B2 patent drawing
  • US8450733B2 patent drawing

AI summary

An oxide semiconductor thin film transistor includes a gate electrode on a substrate, the gate electrode having a first area, a gate insulation layer on the gate electrode, the gate insulation layer covering the gate electrode, an active layer on the gate insulation layer, the active layer having a second area that is smaller than the first area, a source electrode on the active layer, the source electrode contacting a source region of the active layer, a drain electrode on the active layer, the drain electrode contacting a drain region of the active layer, and a passivation layer covering the active layer, the source electrode, and the drain electrode.