Oxide Semiconductor TFT Insulation Pattern Design
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Solution Overview
Problem
Oxide semiconductor TFTs in LCD panels face deterioration due to direct contact with silicon nitride gate insulation layers, leading to degraded electrical characteristics and manufacturing complexities.
Innovation Solution
A display substrate design featuring a protection layer with varying thicknesses to prevent direct contact between the oxide semiconductor pattern and the gate insulation layer, using an etch stopper to maintain the protection layer's integrity and enhance patterning reliability, and a method for manufacturing this substrate that includes sequential deposition and etching of layers to form the oxide semiconductor pattern and etch stopper.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If oxide semiconductor TFT structure is applied directly like a-Si or poly-Si TFT, then manufacturing process is simplified, but electrical characteristics are deteriorated due to direct contact with gate insulation layer
Solution Approach 1:
An insulation pattern is introduced as an intermediary layer between the oxide semiconductor pattern and the gate insulation layer. This insulation pattern prevents direct harmful contact while maintaining the simplified oxide semiconductor TFT structure, thus preserving electrical characteristics without complicating the manufacturing process
2Ease of manufacture
If protection layer is made uniformly thick, then manufacturing process is simple, but patterning reliability is reduced due to unnecessary patterning time
Solution Approach 1:
The protection layer is designed with varying thickness: a first thickness in the first area overlapping the gate electrode and a second thickness (thinner) in the second area adjacent to the first area. This local variation optimizes both manufacturing simplicity and patterning reliability by reducing unnecessary patterning time in the second area while maintaining protection where needed
Data Source
AI summary
A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode.