Oxide Semiconductor TFT Array Panel for High Mobility and Low Cost
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Solution Overview
Problem
Conventional thin film transistors face limitations in charge mobility and manufacturing complexity and cost, with amorphous silicon offering low mobility and polycrystalline silicon requiring costly crystallization processes.
Innovation Solution
A thin film transistor array panel using an oxide semiconductor with a manufacturing method that includes a substrate, data line, light blocking layer, source and drain electrodes, and an insulating layer with specific contact holes, reducing manufacturing complexity and cost while enhancing carrier mobility and aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used as semiconductor, then manufacturing process is simple, but charge mobility is low
Solution Approach 1:
The patent changes the material parameter from conventional silicon (amorphous or polycrystalline) to oxide semiconductor, fundamentally altering the semiconductor's physical and electrical properties to achieve both high charge mobility and simplified manufacturing without requiring crystallization processes
Solution Approach 2:
The patent employs oxide semiconductor as a composite material system that combines the benefits of simple amorphous structure with high charge mobility characteristics, creating a material that outperforms conventional single-phase silicon materials
2Reliability
If polycrystalline silicon is used as semiconductor, then charge mobility is high, but manufacturing cost and complexity increase
Solution Approach 1:
The patent extracts and eliminates the crystallization step from the manufacturing process by using oxide semiconductor instead of polycrystalline silicon, removing the complex and costly crystallization equipment and processes while maintaining high charge mobility through the oxide semiconductor's inherent properties
Solution Approach 2:
The patent adopts oxide semiconductor that can be processed at lower temperatures and with simpler equipment compared to polycrystalline silicon, effectively replacing expensive and complex crystallization processes with more economical manufacturing methods
3Ease of manufacture
If conventional manufacturing process is used, then process is established, but organic layer damage occurs
Solution Approach 1:
The patent changes the etching process parameters by using a two-stage photoresist pattern formation method with different development times, which modifies the etching conditions to be gentler and more selective, thereby preventing damage to the organic layer while still achieving precise contact hole formation
Solution Approach 2:
The patent performs preliminary formation of the photoresist pattern with controlled height differences before the actual etching process, allowing for precise control of etching depth and preventing over-etching that could damage the organic layer, thus protecting the organic layer in advance
Data Source
AI summary
A thin film transistor array panel includes a substrate, a data line and a light blocking layer disposed on the substrate, a thin film transistor disposed on the light blocking layer and including a source electrode, a drain electrode, and an oxide semiconductor layer, and an insulating layer disposed on the substrate and including a first contact hole overlapping a portion of the data line, a second contact hole overlapping a portion of the source electrode, and a third contact hole overlapping a portion of the drain electrode, wherein the first contact hole, the second contact hole, and the third contact hole are arranged in a row in a first direction perpendicular to a direction in which the data line is extended.