Shared-Drain Oxide TFT Structure for Dense BEOL DRAM Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of thin film transistors (TFTs) made of oxide semiconductors into BEOL (Back-End Of Line) processes poses challenges due to the need for low-temperature processing to avoid damaging previously fabricated FEOL (Front-End Of Line) devices, and existing methods lack efficient solutions for forming dense arrays of dynamic random access memory cells with high electrical connectivity.
Innovation Solution
The formation of a semiconductor structure with semiconducting metal oxide plates as access transistors, where source electrodes are formed at the ends and a common drain electrode at the center, integrated with capacitor structures and peripheral circuits on a silicon substrate, using metal interconnects within dielectric layers to ensure efficient electrical connectivity and high density memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-temperature processing is used for TFT fabrication, then FEOL devices are protected from damage, but manufacturing complexity increases due to additional process constraints
Solution Approach 1:
The fabrication process is divided into distinct temperature zones and process stages: FEOL processing occurs at standard temperatures, followed by isolation layer formation at low temperatures, then BEOL integration. This segmentation allows each process to operate under optimal conditions without interfering with previously fabricated devices.
Solution Approach 2:
An isolation dielectric layer is introduced as an intermediary between FEOL and BEOL processes. This layer acts as a protective barrier that enables low-temperature TFT fabrication without damaging underlying FEOL devices, while also providing mechanical support and electrical isolation.
2Productivity
If dense arrays of memory cells are formed, then productivity increases, but manufacturing precision requirements increase due to tighter spacing
Solution Approach 1:
The transistor gate structure transitions from planar to three-dimensional FinFET configuration. This vertical dimension allows for increased effective channel area without proportionally reducing lateral pitch, enabling higher density while maintaining manufacturable feature sizes and relaxed precision requirements.
Solution Approach 2:
Multiple functional layers are nested within the vertical structure: the gate electrode wraps around the semiconductor fin, with source and drain regions positioned at different heights. This nested arrangement maximizes space utilization and enables dense packing while maintaining electrical performance.
3Reliability
If high electrical connectivity is achieved through multiple interconnect layers, then device functionality improves, but device complexity increases
Solution Approach 1:
Interconnect structures utilize vertical vias and three-dimensional routing paths through the dielectric layers. This vertical dimension provides additional routing capacity without increasing lateral footprint, enabling complex electrical connectivity with controlled complexity growth.
Solution Approach 2:
The gate electrode structure serves multiple functions: it acts as the control electrode for the transistor, provides a first interconnect layer for signal routing, and forms part of the capacitive structure in memory cells. This multi-functionality reduces the need for separate dedicated structures, controlling overall complexity.
Data Source
AI summary
A first thin film transistor and a second thin film transistor include a semiconducting metal oxide plate located over a substrate, and a set of electrode structures located on the semiconducting metal oxide plate and comprising, from one side to another, a first source electrode, a first gate electrode, a drain electrode, a second gate electrode, and a second source electrode. A bit line is electrically connected to the drain electrode, and laterally extends along a horizontal direction. A first capacitor structure includes a first conductive node that is electrically connected to the first source electrode. A second capacitor structure includes a second conductive node that is electrically connected to the second source electrode.