Oxide Semiconductor TFT Passivation for Hydrogen-Stable Short Channels
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Solution Overview
Problem
The reduction in pixel size of display devices poses challenges for transistors using oxide semiconductors, as hydrogen penetration into the channel region can cause operational failures due to reduced resistance and mobility, especially when the channel length is 2.0 μm or less.
Innovation Solution
A display device design incorporating a polycrystalline oxide semiconductor layer with a channel length of 2.0 μm or less, utilizing silicon nitride layers as passivation layers deposited at 150° C. to 250° C. to control hydrogen diffusion, ensuring appropriate oxygen and hydrogen supply to maintain transistor functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the channel length is reduced to 2.0 μm or less for high-definition display, then the pixel size is reduced and definition is improved, but hydrogen penetration into the channel region causes operational failures due to reduced resistance and mobility
Solution Approach 1:
Silicon nitride layers are introduced as intermediary passivation layers between the oxide semiconductor layer and the environment. These layers act as mediators that control hydrogen diffusion, preventing harmful hydrogen from reaching the channel region while allowing necessary hydrogen supply to source and drain regions, thus enabling miniaturized transistors to operate reliably
Solution Approach 2:
The deposition temperature of silicon nitride layers is precisely controlled within 150°C to 250°C range. This parameter change optimizes the hydrogen diffusion characteristics of the passivation layer, creating conditions where hydrogen can be supplied to source and drain regions but blocked from penetrating the channel region, resolving the reliability issue in miniaturized transistors
2Reliability
If silicon nitride layers are deposited at 150° C. to 250° C. to control hydrogen diffusion, then hydrogen penetration is minimized and transistor stability is improved, but the deposition process requires precise temperature control
Solution Approach 1:
The deposition temperature parameter is optimized to a specific range (150°C to 250°C) that creates the desired hydrogen diffusion characteristics in silicon nitride layers. This parameter change achieves effective hydrogen control while maintaining process simplicity and manufacturability
3Area of stationary object
If the channel length is reduced for high-definition display, then the aperture ratio is improved, but the transistor mobility and resistance characteristics deteriorate due to hydrogen penetration
Solution Approach 1:
Silicon nitride passivation layers serve as intermediary structures that selectively control hydrogen transport. They enable miniaturized transistors to maintain good mobility and resistance characteristics by preventing hydrogen penetration into the channel region while allowing appropriate hydrogen supply to source and drain regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-definition display devices with stable transistor performance by minimizing hydrogen diffusion, maintaining resistance and mobility, and preventing transistor depletion, even at reduced channel lengths.
Implementation Method 1
utilizing silicon nitride layers as passivation layers deposited at 150° C. to 250° C. to control hydrogen diffusion
Implementation Method 2
control hydrogen diffusion, ensuring appropriate oxygen and hydrogen supply to maintain transistor functionality
Data Source
AI summary
A display device includes an oxide semiconductor layer including a polycrystalline structure, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode opposite to the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer provided in contact with the gate electrode, a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, wherein a channel length of the gate electrode is 2.0 μm or less.