Oxide TFT Display Panel Layout With Lower Electrode and Fewer Masks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current transistor manufacturing processes are limited by high costs and complexity due to the need for crystallization of polysilicon, which results in low charge mobility and high manufacturing costs, while amorphous silicon has low charge mobility, making it difficult to produce high-performance transistors.
Innovation Solution
A transistor display panel design that includes a substrate with a first transistor having a semiconductor, a multi-layer gate electrode, and connecting members, where the gate electrode and connecting members are formed using a half-tone mask to reduce the number of manufacturing processes and time, thereby lowering costs, and utilizing oxide semiconductor materials for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon is used to achieve high charge mobility, then transistor performance is improved, but manufacturing cost increases and process complexity increases due to crystallization requirements
Solution Approach 1:
The patent changes the material parameter from polysilicon to oxide semiconductor, fundamentally altering the semiconductor's electrical properties and enabling high charge mobility without requiring crystallization processes. This parameter change resolves the contradiction by achieving the desired electrical performance through material selection rather than complex processing.
Solution Approach 2:
The patent employs a simpler, more cost-effective oxide semiconductor material that can be deposited using standard sputtering equipment without requiring expensive crystallization furnaces. This approach replaces the expensive polysilicon pathway with a more economical oxide semiconductor solution that achieves comparable or superior performance.
2Reliability
If polysilicon crystallization process is used to improve charge mobility, then transistor performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the semiconductor material parameter from polysilicon to oxide semiconductor, which inherently provides high charge mobility without requiring thermal crystallization. This material parameter change eliminates the need for expensive crystallization equipment and processes, directly reducing manufacturing costs while maintaining or improving charge mobility.
Solution Approach 2:
The patent replaces the mechanical/thermal crystallization process with a physical vapor deposition process (sputtering). Instead of using high-temperature furnaces to crystallize polysilicon, the patent uses magnetron sputtering to deposit oxide semiconductor films, substituting a simpler, more cost-effective manufacturing approach that achieves the same or better electrical performance.
3Ease of manufacture
If amorphous silicon is used to simplify manufacturing process, then manufacturing cost is reduced, but charge mobility decreases
Solution Approach 1:
The patent changes the semiconductor material parameter from amorphous silicon to oxide semiconductor. This material substitution maintains the manufacturing simplicity of amorphous materials (can be deposited at lower temperatures using sputtering) while dramatically improving charge mobility, as oxide semiconductors inherently exhibit higher carrier mobility than amorphous silicon due to their crystalline-like electronic structure within an amorphous matrix.
Data Source
AI summary
A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.