Oxide TFT Array Substrate Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional Oxide TFT array substrates experience parasitic capacitance issues between the gate and source/drain electrodes, leading to flicker in displayed images due to the large overlapping region of these electrodes, which compromises the precision of pixel electrode voltage.
Innovation Solution
Incorporating a first insulation layer between the gate electrode and the gate insulation layer, which increases the distance between the gate and source/drain electrodes, thereby reducing parasitic capacitance and eliminating flicker by increasing the distance between the electrodes of the parallel-plate capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate electrode and source/drain electrodes are positioned close to each other to reduce device area, then the area of the TFT is reduced, but parasitic capacitance increases causing flicker
Solution Approach 1:
An insulation layer is introduced as an intermediary between the gate electrode and source/drain electrodes. This insulation layer acts as a mediator that reduces the parasitic capacitance formed between these electrodes while allowing them to remain in close proximity, thus solving the contradiction between small device area and low parasitic capacitance.
Solution Approach 2:
The dielectric constant parameter of the insulation layer is carefully selected to reduce parasitic capacitance. By changing the material parameter (dielectric constant) of the insulation layer, the parasitic capacitance between gate and source/drain electrodes is reduced without increasing the physical distance between electrodes, maintaining small device area while eliminating flicker.
2Object-affected harmful factors
If the overlapping region between gate and source/drain electrodes is reduced to decrease parasitic capacitance, then parasitic capacitance decreases, but the device area increases
Solution Approach 1:
The insulation layer serves as a mediator that allows the gate and source/drain electrodes to maintain a small overlapping region (reducing parasitic capacitance) while the overall device area remains compact. The insulation layer compensates for the reduced overlapping area by providing electrical isolation.
Solution Approach 2:
The solution moves from a two-dimensional planar arrangement to a three-dimensional structure by adding the insulation layer in the vertical dimension. This allows the electrodes to be positioned closer in the horizontal plane (reducing area) while the insulation layer in the vertical dimension manages the parasitic capacitance issue.
3Object-affected harmful factors
If a first insulation layer is added between gate electrode and gate insulation layer to reduce parasitic capacitance, then parasitic capacitance decreases, but device complexity increases
Solution Approach 1:
The first insulation layer is designed to serve multiple functions: it reduces parasitic capacitance between gate and source/drain electrodes, provides electrical isolation, and can be integrated with existing fabrication processes. By making the insulation layer multi-functional, the added complexity is justified by multiple benefits.
Solution Approach 2:
The thickness and dielectric constant parameters of the first insulation layer are optimized to achieve parasitic capacitance reduction with minimal impact on fabrication complexity. By carefully selecting these parameters, the insulation layer provides the needed electrical isolation without requiring complex additional processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased distance between the gate and source/drain electrodes significantly decreases parasitic capacitance, preventing jump voltage defects and improving the quality of display devices by eliminating flicker and enhancing image stability.
Implementation Method 1
Conventional Oxide TFT array substrates experience parasitic capacitance issues between the gate and source/drain electrodes, leading to flicker in displayed images due to the large overlapping region of these electrodes
Data Source
AI summary
An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes: a gate electrode of a TFT and a gate insulation layer sequentially formed on a base substrate; a semiconductor active layer, an etch stop layer and a source electrode and a drain electrode of the TFT sequentially formed on a part of the gate insulation layer that corresponds to the gate electrode of the TFT, the source and drain electrodes of the TFT are respectively in contact with the semiconductor active layer by way of via holes. The array substrate further includes: a first insulation layer formed between the gate electrode of the TFT and the gate insulation layer and the gate electrode is in contact with the gate insulation layer at a channel region of the TFT between the source electrode and the drain electrode of the TFT.