Oxide Semiconductor Transistor Contacts Without Extra Masking
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Solution Overview
Problem
The manufacturing of bottom-gate transistors with oxide semiconductor layers faces challenges in creating low-resistance regions without increasing cost and takt time, as adding impurities requires additional masking steps, leading to inefficiencies and instability in negative bias temperature performance.
Innovation Solution
The semiconductor device incorporates a method where impurity regions with higher electrical conductivity are formed within the oxide semiconductor layer using a resist layer as a mask, allowing direct contact with conductive layers without the need for additional masking, thereby reducing manufacturing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity regions are formed by adding impurities using a gate electrode as mask, then low-resistance regions are formed in the oxide semiconductor layer, but manufacturing cost and takt time increase due to additional masking steps
Solution Approach 1:
The gate electrode is formed beforehand to serve as a mask for subsequent impurity addition. This preliminary formation of the gate electrode structure enables it to function as a masking layer during impurity region creation, eliminating the need for separate masking steps and reducing manufacturing complexity
Solution Approach 2:
The gate electrode performs dual functions: as the functional gate component of the transistor and as a mask for defining impurity regions. This multi-functionality reduces the total number of process steps and components needed, improving manufacturing efficiency while achieving low-resistance contact regions
2Reliability
If impurity regions are formed using additional masking steps, then low-resistance regions are created, but device complexity and manufacturing cost increase
Solution Approach 1:
The gate electrode is designed to serve multiple purposes: as the operational gate and as a mask for impurity region definition. This eliminates the need for separate masking layers and reduces the overall device structure complexity while ensuring stable electrical characteristics
Solution Approach 2:
The functions of the gate electrode and the mask are merged into a single component. The gate electrode structure is utilized simultaneously for both its electrical function and as a patterning mask during impurity addition, reducing the number of discrete components and process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and reduces the negative bias temperature instability of the transistor by providing stable ohmic contact connections between the oxide semiconductor layer and conductive layers, while also lowering production costs and takt time.
Implementation Method 1
Since the oxide semiconductor has high insulating properties, it is preferable that regions in contact with a source electrode and a drain electrode have low resistance in the oxide semiconductor layer
Implementation Method 2
an impurity element is added into an oxide semiconductor layer using a gate electrode as a mask to form a low-resistance region in the oxide semiconductor layer
Implementation Method 3
an impurity element is added into an oxide semiconductor layer using a gate electrode as a mask
Data Source
AI summary
A semiconductor device includes a first conductive layer, a first insulating layer on the first conductive layer, an oxide semiconductor layer on the first insulating layer, and second and third conductive layers on the oxide semiconductive layer. The oxide semiconductor layer includes a first region, a second region in contact with the second conductive layer, a third region in contact with the third conductive layer, a first impurity region between the first region and the second region, and a second impurity region between the first region and the third region. The first impurity region is in contact with the second conductive layer. The second impurity region is in contact with the third conductive layer. An electrical conductivity of each of the first impurity region and the second impurity region is greater than an electrical conductivity of each of the second region and the third region.