Oxide Semiconductor Transistor Stack for High On-State Current
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high on-state current, high frequency characteristics, reliability, scalability, and low power consumption, particularly in utilizing oxide semiconductors like In—Ga—Zn oxide (IGZO) which require improved electrical and structural properties.
Innovation Solution
A semiconductor device structure is developed with a specific layered configuration of insulators and conductors, including a stacked-layer structure for the oxide layers with varying crystallinity and atomic ratios, and the use of barrier insulators to inhibit impurity diffusion, enhancing the channel formation region and reducing oxygen vacancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If oxide semiconductors like IGZO are used in transistors, then power consumption is reduced due to extremely low off-state current, but on-state current is insufficient for high-performance applications
Solution Approach 1:
The patent applies local quality by creating a multi-layer oxide semiconductor structure where different layers have different compositions and properties. Specifically, an In-Ga-Zn-O layer is combined with an In-Al-Zn-O layer, where each layer contributes different characteristics: the In-Ga-Zn-O layer provides low off-state current while the In-Al-Zn-O layer enhances on-state current and crystallinity. This local differentiation of material properties within the semiconductor layer resolves the contradiction between low power consumption and high on-state current.
Solution Approach 2:
The patent employs composite materials by stacking multiple oxide semiconductor layers with different compositions. The composite structure consists of an In-Ga-Zn-O layer and an In-Al-Zn-O layer, where the combination of these materials achieves both low off-state current (from the In-Ga-Zn-O layer) and high on-state current (enhanced by the In-Al-Zn-O layer with higher crystallinity). This composite approach allows simultaneous optimization of power consumption and driving current capability.
2Power
If oxide semiconductor layers are formed with higher crystallinity to improve on-state current, then manufacturing complexity and process control difficulty increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the atomic ratios of elements in different oxide layers. The In-Al-Zn-O layer is designed with specific atomic ratios (In:Al:Zn = 1:(0.2-0.8):(0.2-0.8)) to optimize crystallinity and on-state current. By controlling these compositional parameters during deposition, the patent achieves high crystallinity without requiring overly complex process equipment, as the composition control can be integrated into existing sputtering or ALD processes.
Solution Approach 2:
The patent segments the oxide semiconductor into multiple layers with distinct functions. The bottom In-Ga-Zn-O layer is optimized for low off-state current, while the top In-Al-Zn-O layer is optimized for high crystallinity and on-state current. This segmentation allows each layer to be independently optimized for its specific function, reducing the overall process complexity compared to attempting to optimize a single uniform layer for both properties simultaneously.
3Reliability
If multiple oxide layers with different compositions are stacked to enhance performance, then device reliability improves, but structural complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies local quality by assigning specific compositional characteristics to specific layers. The In-Ga-Zn-O layer is designed with Ga content optimized for stability and low off-state current, while the In-Al-Zn-O layer is designed with Al content optimized for crystallinity enhancement and on-state current. This localized optimization of material quality in each layer improves overall device reliability while keeping the structural complexity manageable through a simple two-layer configuration.
Data Source
AI summary
A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.