Stacked Oxide Transistor Memory Circuit for Low-Leakage Readout
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving low off-state current, high reliability, low power consumption, reduced manufacturing costs, and smaller size while maintaining effective data readout capabilities.
Innovation Solution
A semiconductor device structure incorporating a silicon substrate with multiple transistor layers, including a first layer using silicon channels and a second layer using metal oxide channels, featuring a correction circuit to manage threshold voltage and bit lines arranged perpendicularly, allowing for efficient data storage and retrieval with reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If metal oxide transistors are used in the second transistor layer, then off-state current is reduced and power consumption is lowered, but device complexity increases due to multi-layer stacking
Solution Approach 1:
The patent transitions from planar single-layer transistor arrangement to three-dimensional multi-layer stacking, where the first transistor layer (silicon-based) and second transistor layer (metal oxide-based) are vertically stacked over the silicon substrate. This dimensional change enables low off-state current through metal oxide transistors while managing complexity through systematic interlayer connection design.
Solution Approach 2:
The patent employs composite material strategy by integrating two different transistor types: silicon-based transistors in the first layer and metal oxide-based transistors in the second layer. Each material type contributes its superior characteristics - silicon provides mature工艺 compatibility while metal oxide provides ultra-low off-state current, creating a composite device system that balances performance and complexity.
2Volume of moving object
If multiple transistor layers are stacked, then device integration density is improved and size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the integrated circuit into distinct functional layers: a first transistor layer for core logic operations and a second transistor layer for specialized functions requiring ultra-low leakage. This segmentation allows each layer to be optimized independently with appropriate transistor types, achieving high integration density while managing manufacturing precision through modular fabrication approaches.
Solution Approach 2:
The stacked transistor layer structure serves multiple functions simultaneously: the first silicon-based layer handles high-speed logic operations, while the second metal oxide layer provides ultra-low leakage storage or specialized logic functions. This multi-functionality approach maximizes the utility of the compact three-dimensional structure, achieving high integration density with justified manufacturing complexity.
3Reliability
If correction circuits are added to hold threshold voltage, then data readout reliability is improved, but device area increases
Solution Approach 1:
The patent merges the correction circuit functionality into the existing multi-layer transistor structure by utilizing transistors from both the first and second layers. The correction circuits are integrated alongside the main logic circuits, sharing common interlayer connection structures and bit line infrastructure. This merging approach provides threshold voltage compensation for reliable data readout while minimizing additional area overhead through resource sharing.
Data Source
AI summary
A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.