Oxide Semiconductor Transistor Withstand Voltage

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Solution Overview

Problem

Current transistors with oxide semiconductors face challenges in achieving high withstand voltage, high manufacturing yield, low parasitic capacitance, high frequency characteristics, and stable electrical characteristics while maintaining low off-state current and parasitic capacitance.

Innovation Solution

The semiconductor device incorporates a specific structure with conductors and insulators, including a multilayer film with metal oxides and fluorine, and a deposition process that minimizes hydrogen release, enhancing the transistor's electrical properties and manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a transistor includes an oxide semiconductor formed by sputtering method, then it can be used for large display devices and reduce capital investment, but it faces challenges in achieving high withstand voltage and stable electrical characteristics

Engineering Contradiction:
Improvemanufacturing easeVSAvoidelectrical characteristics stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies parameter changes by controlling the thickness of the oxide semiconductor layer within a specific range (5 nm to 50 nm) and adjusting the composition ratios of metal elements (In:Ga:Zn = 1:1:1 to 1:3:5) to achieve both ease of manufacture and stable electrical characteristics. The gate voltage is also controlled within specific ranges (10V to 20V) to stabilize the transistor performance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses composite materials by combining oxide semiconductor layers with specific metal element combinations (In-Ga-Zn-O) and integrating them with gate electrodes, insulating layers, and conductive layers. This composite structure enables the transistor to achieve high withstand voltage and stable electrical characteristics while maintaining manufacturing feasibility through sputtering methods.

Inventive Principle:
Principle #40Composite materials

2Reliability

If the oxide semiconductor layer thickness is increased to improve withstand voltage, then electrical breakdown resistance improves, but parasitic capacitance increases

Engineering Contradiction:
Improvewithstand voltageVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent optimizes the oxide semiconductor layer thickness to a specific range (5 nm to 50 nm) to achieve the right balance between withstand voltage and parasitic capacitance. This parameter optimization ensures that the transistor has sufficient electrical breakdown resistance while maintaining low parasitic capacitance for high-frequency operation.

Inventive Principle:
Principle #35Parameter changes

3Object-generated harmful factors

If conventional oxide semiconductor transistors are used, then low off-state current is achieved, but high frequency characteristics and manufacturing yield are compromised

Engineering Contradiction:
Improveoff-state currentVSAvoidmanufacturing yield
Core Design Contradiction:
Object-generated harmful factorsVSProductivity

Solution Approach 1:

The patent changes key parameters including the oxide semiconductor composition (In:Ga:Zn ratio), layer thickness (5-50 nm), and gate voltage (10-20V) to simultaneously achieve low off-state current and high manufacturing yield. These parameter optimizations enable consistent transistor performance across large-scale production.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary action by performing plasma treatment on the oxide semiconductor layer before final transistor formation to remove contaminants and stabilize surface properties. This preliminary step ensures low off-state current and improves manufacturing yield by preventing defects during subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

4Ease of manufacture

If the transistor structure is simplified to improve manufacturing ease, then production efficiency increases, but electrical characteristics and frequency response deteriorate

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidfrequency characteristics
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent optimizes the thickness of the oxide semiconductor layer (5-50 nm) and controls the gate voltage (10-20V) to achieve high-frequency characteristics without requiring complex transistor structures. This parameter optimization allows the simplified structure to maintain excellent frequency response.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in a transistor with improved withstand voltage, manufacturing yield, frequency characteristics, and stable electrical performance, while reducing parasitic capacitance and off-state current.

Implementation Method 1

An oxide semiconductor can be formed by a sputtering method or the like

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS10950734B2Semiconductor device and manufacturing method thereof
Publication Date: 2021.03.16 SEMICON ENERGY LAB CO LTD
  • US10950734B2 patent drawing
  • US10950734B2 patent drawing
  • US10950734B2 patent drawing

AI summary

A semiconductor device includes a semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The first conductor and the semiconductor partly overlap with each other with the first insulator positioned therebetween. The second conductor and the third conductor have regions in contact with the semiconductor. The semiconductor has a region in contact with the second insulator. The fourth insulator has a first region and a second region. The first region is thicker than the second region. The first region has a region in contact with the second insulator. The second region has a region in contact with the third insulator. The fourth conductor and the second insulator partly overlap with each other with the fourth insulator positioned therebetween.