Non-volatile Memory Cell Array in P-well Deep N-well Structure

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing non-volatile memory cell arrays require high peak positive voltages for erase operations, which necessitate substantial space for high voltage generation and regulation circuitry, making them inefficient in terms of space and power usage.

Innovation Solution

A non-volatile memory cell array formed in a p-well within a deep n-well in a p-substrate, where a negative voltage is applied to the p-well during erase operations, reducing the peak positive voltage required for erasing and thereby minimizing the size and power of the high voltage generation block.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high peak positive voltage is applied during erase operations, then erase effectiveness is improved, but the size and power consumption of high voltage generation circuitry increases

Engineering Contradiction:

Improveerase effectivenessVSAvoidhigh voltage generation circuitry area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The voltage generation function is segmented between the p-well (which generates negative voltage) and the high voltage generation block (which only needs to generate reduced positive voltage). This segmentation allows the high voltage generation circuitry to be smaller while maintaining erase effectiveness through the combined voltage effect.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the voltage parameter by applying negative voltage to the p-well, which transforms the erase operation from requiring high positive voltage alone to requiring a combination of negative p-well voltage and reduced positive voltage, thereby reducing the peak positive voltage requirement.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If high peak positive voltage is applied during erase operations, then erase effectiveness is improved, but power consumption increases

Engineering Contradiction:

Improveerase effectivenessVSAvoidhigh voltage generation power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The power consumption is segmented by having the p-well handle the negative voltage generation (which can be done more efficiently) and the high voltage generation block handling only the reduced positive voltage portion, thereby reducing total power consumption while maintaining erase effectiveness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

By changing the voltage parameters to include negative p-well voltage, the power consumption is reduced because the high voltage generation block no longer needs to generate the full peak positive voltage alone, distributing the power burden more efficiently.

Inventive Principle:

Principle #35Parameter changes

3Area of stationary object

If negative voltage is applied to p-well, then peak positive voltage requirement is reduced, but device complexity increases

Engineering Contradiction:

Improvehigh voltage generation block sizeVSAvoidwell structure complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The p-well is nested within the deep n-well, which is nested within the p-substrate, creating a layered structure that enables negative voltage application to the p-well while maintaining compatibility with the overall device architecture. This nested structure manages complexity through hierarchical organization.

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The deep n-well acts as an intermediary between the p-well and the p-substrate, enabling the p-well to be isolated and biased at negative voltage while maintaining proper electrical connections and isolation. This intermediary structure manages the complexity of negative voltage implementation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the peak positive voltage needed for erase operations, leading to a more compact and power-efficient design by allowing the use of lower voltages during erase operations, thus optimizing space and power consumption.

Implementation Method 1

electrons on floating gate 20 to tunnel through the intermediate insulation from floating gate 20 to word line terminal 22 via Fowler-Nordheim (FN) tunneling

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Data Source

PatentUS20220375952A1Non-volatile memory cell array formed in a p-well in a deep n-well in a p-substrate

Publication Date: 2022.11.24 SILICON STORAGE TECHNOLOGY INC

AI summary

Numerous embodiments are disclosed of a non-volatile memory cell array formed in a p-well, which is formed in a deep n-well, which is formed in a p-substrate. During an erase operation, a negative voltage is applied to the p-well, which reduces the peak positive voltage required to be applied to the cells to cause the cells to erase.