Semiconductor Package Structure With Back-Side Enhancement Against Warpage

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Solution Overview

Problem

Semiconductor package structures face issues such as warpage due to mismatched thermal expansion coefficients, leading to solder bridging and reduced heat dissipation, as well as uneven surfaces causing air trapping and reliability problems during thermal processes.

Innovation Solution

Incorporating a back-side enhancing layer with specific mechanical and thermal properties, along with a planarizing process to create a smooth surface, to address warpage and improve heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a conventional semiconductor package structure is used, then the manufacturing process is simple, but warpage occurs due to mismatched thermal expansion coefficients

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidpackage structure warpage

Core Design Contradiction:

Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The patent applies composite materials by integrating an enhancement layer with specific mechanical and thermal properties into the package structure. This layer is composed of materials selected to match the coefficient of thermal expansion (CTE) with the semiconductor die, creating a composite structure that resolves the warpage issue caused by CTE mismatch while maintaining manufacturing feasibility

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The patent changes the physical and mechanical parameters of the package structure by introducing an enhancement layer with specifically controlled properties (CTE matching the die, appropriate thickness, and mechanical strength). This parameter modification directly addresses the warpage problem without fundamentally changing the manufacturing process

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If the package structure undergoes thermal processes, then soldering and encapsulation can be performed, but air trapping occurs due to uneven surfaces

Engineering Contradiction:

Improvethermal process capabilityVSAvoidair trapping during thermal processes

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by performing a planarizing process on the enhancement layer before subsequent thermal processes. This pre-treatment creates a flat surface that prevents air trapping during later soldering and encapsulation operations, ensuring reliability without sacrificing manufacturing capability

Inventive Principle:

Principle #10Preliminary action

3Productivity

If the package structure is subjected to thermal expansion, then assembly can proceed, but solder bridging occurs due to warpage

Engineering Contradiction:

Improveassembly rateVSAvoidsolder bridging

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The enhancement layer acts as a composite material component that compensates for thermal expansion differences. By matching the CTE of the semiconductor die, this layer prevents warpage during thermal expansion, thereby avoiding solder bridging while maintaining high assembly productivity

Inventive Principle:

Principle #40Composite materials

4Temperature

If heat dissipation is required, then thermal management can be implemented, but heat dissipation efficiency is reduced due to warpage

Engineering Contradiction:

Improveheat dissipation capabilityVSAvoidheat dissipation efficiency

Core Design Contradiction:

TemperatureVSLoss of energy

Solution Approach 1:

The patent inverts the conventional approach by placing the thermal management enhancement on the back side of the semiconductor die rather than the front. This back-side enhancement layer provides both mechanical support to prevent warpage and thermal conduction pathways, improving heat dissipation efficiency without interfering with the active circuitry

Inventive Principle:

Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively suppresses warpage, reduces solder bridging, enhances heat dissipation, and ensures reliable semiconductor die placement, thereby improving the overall performance and reliability of the package structure.

Implementation Method 1

a back-side enhancing layer formed over a back-side of the semiconductor die... capable of suppressing warpage of the package structure

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

a planarizing process to create a smooth surface

Methodology Applied

Scientific EffectPlanarization:

Implementation Method 3

enhances heat dissipation

Methodology Applied

Scientific EffectHeat dissipation: Conduction (thermal)

Data Source

PatentUS12599018B2Package structure with enhancement structure and manufacturing method thereof

Publication Date: 2026.04.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A package structure includes a die, a first redistribution circuit structure, a first redistribution circuit structure, a second redistribution circuit structure, an enhancement layer, first conductive terminals, and second conductive terminals. The first redistribution circuit structure is disposed on a rear side of the die and electrically coupled to thereto. The second redistribution circuit structure is disposed on an active side of the die and electrically coupled thereto. The enhancement layer is disposed on the first redistribution circuit structure. The first redistribution circuit structure is disposed between the enhancement layer and the die. The first conductive terminals are connected to the first redistribution circuit structure. The first redistribution circuit structure is between the first conductive terminals and the die. The second conductive terminals are connected to the second redistribution circuit structure. The enhancement layer is between the second conductive terminals and the second redistribution circuit structure.