Semiconductor Package Structure With Buffer Layer for Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing packaging techniques for semiconductor chips in high-performance computing systems face challenges in achieving miniaturization, higher speed, and better electrical performance, particularly in terms of signal integrity and power integrity, while maintaining cost-effectiveness.
Innovation Solution
A package structure is formed with a redistribution structure on a tape frame, including multiple layers of conductive and dielectric patterns, and substrate components with build-up structures, where buffer materials are used to relieve stress and prevent cracking, followed by encapsulation for structural support and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging techniques are used, then manufacturing cost is reduced, but electrical performance and signal integrity deteriorate
Solution Approach 1:
The packaging structure is divided into multiple functional layers including substrate, build-up structure with conductive patterns, dielectric layers, and encapsulant. This segmentation allows each layer to be optimized for specific electrical performance requirements while maintaining manufacturing feasibility through standardized processes for each segment.
Solution Approach 2:
The patent transitions from conventional 2D planar packaging to a 3D vertical architecture with stacked conductive patterns, dielectric layers, and through-substrate vias. This dimensional change enables shorter signal paths, reduced parasitic effects, and improved signal integrity while maintaining a compact footprint suitable for cost-effective manufacturing.
2Volume of moving object
If miniaturization is pursued, then device density is improved, but stress and cracking increase
Solution Approach 1:
A stress relief structure is incorporated into the packaging design to compensate for thermal expansion mismatches and mechanical stresses before they cause cracking. This preventive measure allows miniaturization to be pursued while maintaining structural integrity through built-in stress compensation mechanisms.
Solution Approach 2:
The packaging employs composite material structures with different dielectric layers, conductive materials, and encapsulants having complementary mechanical and thermal properties. This composite approach balances the conflicting requirements of miniaturization and stress resistance by combining materials that individually address different aspects of the contradiction.
3Reliability
If higher speed and better electrical performance are achieved, then signal integrity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent optimizes electrical parameters such as trace impedance, via dimensions, and dielectric thickness to achieve high-speed signal integrity. These parameter changes are implemented within existing manufacturing process capabilities, avoiding the need for entirely new manufacturing techniques while still achieving superior electrical performance.
Solution Approach 2:
The build-up structure serves as an intermediary layer between the substrate and overlying components, providing controlled impedance pathways, signal routing, and electrical connections. This intermediary structure enables high-speed signal transmission while using standard PCB fabrication processes, thereby managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves excellent electrical performance with reduced cracking and stress, enabling high bandwidth and low-cost packaged structures suitable for high-performance computing applications.
Implementation Method 1
buffer materials are used to relieve stress and prevent cracking
Data Source
AI summary
A manufacturing method of a package structure includes: forming a redistribution structure which includes first bump portions formed over an outermost dielectric layer; forming a buffer material on the outermost dielectric layer, where the buffer material includes a reflowable material and a polymer material; disposing a substrate component on the redistribution structure, where second bump portions of the substrate component contact the first bump portions, and the buffer material covers the first and second bump portions; reflowing the first and second bump portions to form conductive joints, where after the reflowing, the polymer material of the buffer material remains to form a buffer layer; and forming an insulating encapsulation on the redistribution structure to cover the substrate component, where the insulating encapsulation extends into a gap between the redistribution structure and the substrate component to cover the buffer layer and the conductive joints.