Package Carrier Substrate With Integrated Encapsulation Layer
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Solution Overview
Problem
Conventional chip packaging processes are complex, time-consuming, costly, and have low yield, failing to meet the demands for small, lightweight, and integrated circuit designs.
Innovation Solution
A package carrier substrate and manufacturing method involving an insulating substrate with multiple wiring layers, conductive vias, pads, and structures, where the encapsulation layer is formed between substrate units to create separate packages, reducing processing complexity and cost while increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip packaging process is used with multiple processing steps including etching, then chip structures can be sealed and connected, but the process becomes complicated and processing time increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the encapsulation layer to cover the chip structures before any etching or cutting operations. The encapsulation layer is formed to extend over the chip structures and is then patterned to expose only the conductive structures, eliminating the need for subsequent etching steps. This preliminary formation of the encapsulation layer in a comprehensive manner before selective removal simplifies the overall process while ensuring reliable sealing and protection.
2Reliability
If conventional chip packaging process with multiple steps is used, then chip structures are sealed and connected, but processing time becomes long
Solution Approach 1:
The patent merges multiple sequential operations into a more integrated process flow. The encapsulation layer formation, patterning, and the subsequent cutting of the package substrate are coordinated such that the encapsulation layer already covers and protects the chip structures when cutting occurs. This merging of operations eliminates the need for separate etching steps and reduces the total number of process cycles, thereby reducing processing time while maintaining reliable sealing.
3Reliability
If conventional chip packaging process is used, then chip structures can be sealed, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the etching step from the conventional packaging process. By designing the encapsulation layer to be formed and patterned in advance, the process removes the need for chemical etching operations, which reduce material waste, decrease processing complexity, and lower manufacturing costs. The encapsulation layer is directly patterned to expose conductive structures without requiring additional etching chemistry or equipment.
4Reliability
If conventional chip packaging process is used, then chip structures are sealed and connected, but manufacturing yield becomes poor
Solution Approach 1:
The patent applies preliminary action by forming the encapsulation layer to completely cover and protect the chip structures before any cutting or separation operations. This preliminary protective coverage prevents damage to the chip structures during subsequent manufacturing steps, reducing defect rates and improving yield. The encapsulation layer is patterned to expose only the necessary conductive structures, ensuring proper electrical connections while maintaining protection during handling and assembly.
Data Source
AI summary
A package carrier structure includes an insulating substrate, a first wiring layer, a second wiring layer, at least one conductive via, a plurality of first and second conductive pads, a first insulating layer, a plurality of first and second conductive structures, and an encapsulated layer. The first and second wiring layers are disposed on the upper and lower surfaces of the insulating substrate respectively. The conductive via penetrates through the insulating substrate and electrically connected to the first and second wiring layers. The first and second conductive pads are disposed on the upper surface and electrically connected to the first wiring layer. The first insulating layer is disposed on the upper surface and exposing the first and second conductive pads. The first and second conductive structures are disposed on the first and second conductive pads respectively. The lower surface of the insulating substrate is covered by the encapsulation layer.