Package Structure with Conductive Bumps for Fine-Pitch Wiring
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Solution Overview
Problem
Conventional wafer-level packaging processes face challenges in fabricating fine-pitch wiring redistribution layers due to the need for costly and precise adhesive layers, which increase fabrication costs and complicate achieving high surface flatness.
Innovation Solution
A package structure and method involving a conductive pattern layer with bump and wiring regions, dielectric materials, and a blocking frame, where conductive pillars are formed to connect bumps and wires, allowing for high-density circuit layouts without the need for costly adhesives, and enabling the use of ordinary dielectric materials to surround connecting terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography means is used to fabricate fine-pitch-wiring RDL, then fine-pitch wires can be realized, but the upper surface of the semi-finished package structure must be very flat which requires costly adhesive and slow precise bonding
Solution Approach 1:
The patent divides the package structure into distinct functional regions: a bump region with conductive bumps for fine-pitch connections and a wiring region with conductive wires for signal routing. This segmentation allows each region to be optimized independently - the bump region achieves fine-pitch precision while the wiring region provides cost-effective interconnection, eliminating the need for expensive adhesive layers required in conventional uniform structures.
Solution Approach 2:
The patent applies different structural characteristics to different regions of the package. The bump region uses vertical conductive bumps with precise positioning for fine-pitch wiring, while the wiring region uses planar conductive traces. This local differentiation allows fine-pitch precision to be achieved only where necessary (at the bump region) rather than requiring the entire upper surface to be perfectly flat, thereby reducing fabrication costs.
2Manufacturing precision
If costly adhesive is used to achieve high surface flatness, then fine-pitch wiring can be fabricated, but the fabrication cost increases
Solution Approach 1:
The patent segments the surface structure into bump regions requiring high precision and wiring regions where cost-effectiveness is prioritized. By using conductive bumps with precise positioning in the bump region rather than relying on adhesive layers for overall surface flatness, the patent achieves the necessary precision for fine-pitch wiring without incurring the high costs associated with adhesive materials and slow bonding processes.
Solution Approach 2:
The patent replaces expensive adhesive materials with a more cost-effective structure based on conductive bumps and dielectric materials. The bumps serve as both mechanical support and electrical connection elements, eliminating the need for separate adhesive layers while providing the necessary positioning accuracy for fine-pitch wiring fabrication.
3Reliability
If adhesive layer is used to bond semiconductor die and electronic component, then connection is achieved, but the process becomes slow and precise which increases fabrication cost
Solution Approach 1:
The patent extracts the bonding function from the adhesive layer and integrates it into the conductive bump structure itself. The bumps provide both mechanical attachment and electrical connection in a single element, eliminating the separate adhesive bonding step. This integration significantly speeds up the fabrication process while maintaining reliable connections between the semiconductor die, electronic components, and substrate.
Solution Approach 2:
The patent merges the mechanical bonding function and electrical connection function into a single integrated structure using conductive bumps. Instead of using separate adhesive layers for bonding and separate trace structures for electrical connection, the bumps simultaneously provide both functions, thereby eliminating slow adhesive bonding processes and reducing overall fabrication time and cost.
Data Source
AI summary
This disclosure provides a package structure and its fabrication method. The package structure includes: a conductive pattern layer having a bump region and a wiring region, the bump region comprising a plurality of conductive bumps and a first dielectric material surrounding the plurality of conductive bumps, the wiring region comprising a plurality of first conductive wires and a second dielectric material covering and surrounding the plurality of first conductive wires; a circuit device with a plurality of connecting terminals disposed on the bump region, each of the connecting terminals corresponding with one of the conductive bumps; an insulation sealant formed on the second dielectric material and around sidewalls of the circuit device; and a third dielectric material covering the circuit device and the wiring region.