Package-in-Packages Semiconductor Module Integration

Solution Overview

Problem

Conventional semiconductor packages are unable to support multiple semiconductor chips or tiny chips due to size constraints, limiting their integration and compliance with standard packaging dimensions.

Innovation Solution

A semiconductor device comprising a leadframe with a die paddle and a semiconductor module, where the module includes multiple semiconductor chips embedded in an encapsulant and connected to leads via interconnects, allowing for non-standard package configurations that comply with standard dimensions, such as JEDEC standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional packaging is used, then standard packaging dimensions are maintained, but multiple semiconductor chips or tiny chips cannot be supported

Engineering Contradiction:

Improvenumber of chipsVSAvoidpackage configuration flexibility

Core Design Contradiction:

Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent embeds a non-standard semiconductor package containing multiple chips within a standard-sized leadframe package. The inner package (first encapsulant with multiple chips) is nested inside the outer standard package (second encapsulant), allowing multiple chips to be housed within standard dimensions. This nesting approach enables high integration without violating external dimensional standards.

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent transitions from a single-layer chip arrangement to a three-dimensional stacked configuration. Multiple semiconductor chips are arranged vertically or in multiple layers within the package, utilizing the Z-dimension (height) rather than only the X-Y plane. This dimensional change allows more chips to be packed into the same footprint area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If multiple chips are integrated in a single package, then chip integration is improved, but packaging costs increase

Engineering Contradiction:

Improvenumber of chipsVSAvoidpackaging cost

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent divides the packaging system into two independent segments: an inner non-standard package containing multiple chips (first encapsulant) and an outer standard leadframe package (second encapsulant). This segmentation allows the inner package to be optimized for high integration while the outer package maintains standardization, enabling cost-effective manufacturing by separating the complex multi-chip assembly from the standardized external interface.

Inventive Principle:

Principle #1Segmentation

3Quantity of substance

If non-standard package configurations are used, then multiple chips can be supported, but compatibility with existing standards is reduced

Engineering Contradiction:

Improvenumber of chipsVSAvoidstandard compliance

Core Design Contradiction:

Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent embeds a non-standard semiconductor package containing multiple chips within a standard-sized leadframe package. The inner package (first encapsulant with multiple chips) is nested inside the outer standard package (second encapsulant), allowing multiple chips to be housed within standard dimensions. This nesting approach enables high integration without violating external dimensional standards.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS9147628B2Package-in-packages and methods of formation thereof

Publication Date: 2015.09.29 INFINEON TECH AUSTRIA AG

AI summary

In accordance with an embodiment of the present invention, a semiconductor device includes a leadframe having a plurality of leads and a die paddle and a semiconductor module attached to the die paddle of the leadframe. The semiconductor module includes a first semiconductor chip disposed in a first encapsulant. The semiconductor module has a plurality of contact pads coupled to the first semiconductor chip. The semiconductor device further includes a plurality of interconnects coupling the plurality of contact pads with the plurality of leads, and a second encapsulant disposed at the semiconductor module and the leadframe.