Package-Level Backside Metallization for Thermal Management
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Solution Overview
Problem
Legacy techniques for applying backside metallization (BSM) layers at the wafer-level limit flexibility in downstream manufacturing and make it difficult to use solder thermal interface materials (STIM) efficiently, especially with thinned dies, due to increased costs and process complexities.
Innovation Solution
Applying the BSM layer at the package-level instead of the wafer-level, allowing for the use of polymer thermal interface materials (PTIM) or STIM with thinned dies, enabling more flexible manufacturing and improved thermal performance by forming inter-metallic compound joints between the die and integrated heat sinks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If BSM layer is applied at wafer-level, then manufacturing process is standardized, but flexibility in downstream manufacturing is limited and costs increase
Solution Approach 1:
The patent divides the manufacturing process into distinct stages: wafer-level processing for die attachment, and package-level processing for BSM layer application. This segmentation allows different manufacturing approaches to be used at different stages, achieving both standardization where needed and flexibility where required. The BSM layer is applied to individual packages rather than entire wafers, enabling selective thermal management solutions.
Solution Approach 2:
The patent introduces dynamic adaptability by allowing the BSM layer application to be selected based on specific package requirements. Some packages receive BSM layers for high-power thermal management, while others use alternative thermal interface materials. This dynamic approach enables the manufacturing process to adapt to different power requirements and thermal management needs.
2Device complexity
If BSM layer is applied at wafer-level, then process integration is achieved, but it becomes difficult to use STIM efficiently with thinned dies
Solution Approach 1:
The patent applies the BSM layer at the package level after die attachment, which is a preliminary action that prepares the surface for subsequent STIM application. This timing allows the die to be properly thinned and positioned before the metallization layer is applied, ensuring optimal conditions for STIM bonding and thermal contact.
3Ease of manufacture
If BSM layer is applied uniformly across all dies, then manufacturing simplicity is maintained, but lower-cost chips with PTIM cannot be used for lower-power applications
Solution Approach 1:
The patent implements local quality by applying BSM layers only to specific packages that require high-power thermal management, rather than uniformly to all dies. This allows different thermal interface solutions (STIM for high-power, PTIM for lower-power) to be used in different locations based on actual requirements, optimizing both performance and cost.
4Productivity
If wafer-level BSM process is used, then throughput is high, but it increases costs and process complexities for thinned dies
Solution Approach 1:
The patent segments the BSM application process from wafer-level to package-level processing. This segmentation reduces process complexity for thinned dies by allowing simpler, more adaptable manufacturing steps at the package level, while maintaining high throughput through efficient die attachment processes at the wafer level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the use of lower-cost chips with PTIM for lower-power applications and higher-power chips with STIM, enhancing thermal performance and manufacturing flexibility by decoupling the BSM application from the type of thermal interface material used, and allowing for efficient thermal management in microelectronic packages.
Implementation Method 1
a backside metallization (BSM) layer may be used to enable the STIM to form an inter-metallic compound (IMC) joint with a die
Data Source
AI summary
Embodiments may relate to a microelectronic package that includes a die and a backside metallization (BSM) layer positioned on the face of the die. The BSM layer may include a feature that indicates that the BSM layer was formed on the face of the die by a masked deposition technique. Other embodiments may be described or claimed.