Package-on-Package Structure With Segmented Via Design
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density integration and efficient packaging due to limitations in current three-dimensional integration technologies, particularly in maintaining structural integrity and preventing via collapse in package-on-package structures.
Innovation Solution
The proposed solution involves a method for fabricating a package-on-package (PoP) structure using a redistribution layer with alternating dielectric and conductive layers, where first and second through insulator vias are strategically placed within the insulating encapsulant to enhance structural integrity, with the second through insulator vias having a greater aspect ratio and size in the peripheral area to prevent via collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional three-dimensional integration technology is used, then integration density can be increased, but via collapse and structural integrity issues occur
Solution Approach 1:
The patent divides the via structure into multiple segments: through insulator vias, partial insulator vias, and conductive plugs. This segmentation allows each via component to be optimized independently, with through insulator vias providing structural support and partial insulator vias enabling electrical connections, thereby preventing via collapse while maintaining high integration density
Solution Approach 2:
The patent applies different properties to different regions of the package structure. Through insulator vias are positioned in specific locations where structural support is needed, while partial insulator vias are placed where electrical connections are required. This local differentiation ensures that structural integrity is maintained in critical areas while achieving high integration density overall
2Area of stationary object
If package size is reduced, then area utilization improves, but structural integrity and via stability deteriorate
Solution Approach 1:
The patent implements a nested via structure where partial insulator vias are positioned within or adjacent to through insulator vias. This nesting allows compact arrangement of multiple via functions in a small area, maintaining via stability through the outer through insulator vias while enabling electrical connections via the inner partial insulator vias, thus achieving high area utilization without sacrificing structural integrity
Solution Approach 2:
The patent transitions from two-dimensional planar arrangements to three-dimensional vertical stacking of vias and conductive plugs. By utilizing the vertical dimension, multiple electrical connections can be achieved within a compact footprint, maintaining via stability through properly designed via structures while significantly improving area utilization
Data Source
AI summary
A package structure includes a first semiconductor die, an insulating encapsulant, a plurality of first through insulator vias, a plurality of second through insulator vias, and a redistribution layer. The insulating encapsulant is encapsulating the first semiconductor die. The first through insulator vias are located in a central area of the insulating encapsulant surrounding the first semiconductor die. The second through insulator vias are located in a peripheral area of the insulating encapsulant surrounding the plurality of first through insulator vias located in the central area, wherein an aspect ratio of the plurality of second through insulator vias is greater than an aspect ratio of the plurality of first through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the first semiconductor die, the plurality of first through insulator vias and the plurality of second through insulator vias.