Semiconductor Package Open Region Layout for Impedance Continuity

Solution Overview

Problem

Semiconductor packages experience characteristic degradation due to conductive bumps connected to signal lines, leading to impedance issues and reduced performance in high-speed applications.

Innovation Solution

Incorporating a metal pattern layer with an open region that overlaps non-contact pads to reduce capacitance and stub influence, thereby minimizing impedance discontinuity and improving signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive bumps are connected to signal lines on the main board, then electrical connection is achieved, but impedance discontinuity and signal integrity degradation occur

Engineering Contradiction:

Improvesignal integrityVSAvoidimpedance discontinuity

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the harmful capacitive effect by creating an open region that removes metal patterns from specific areas. This extraction eliminates the parasitic capacitance between non-contact bumps and adjacent metal layers, thereby removing the source of impedance discontinuity while preserving the necessary electrical connections through contact pads.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by creating a non-uniform metal pattern distribution. The open region is strategically positioned to remove metal only where it creates harmful capacitance with non-contact bumps, while maintaining metal patterns in other areas for electrical connectivity. This localized modification optimizes signal integrity without compromising overall package functionality.

Inventive Principle:

Principle #3Local quality

2Weight of moving object

If electronic devices are made lighter, thinner, and smaller, then device portability is improved, but semiconductor package performance and capacitance requirements increase

Engineering Contradiction:

Improvedevice weightVSAvoidsemiconductor package performance

Core Design Contradiction:

Weight of moving objectVSReliability

Solution Approach 1:

The patent changes the geometric parameters of the metal pattern layer by introducing an open region. This parameter modification reduces the capacitance value to appropriate levels for high-speed applications in miniaturized devices, allowing the package to meet performance requirements despite smaller dimensions and reduced weight.

Inventive Principle:

Principle #35Parameter changes

3Quantity of substance

If metal pattern layers are added to increase capacitance, then high-capacitance requirement is met, but impedance discontinuity and signal degradation worsen

Engineering Contradiction:

ImprovecapacitanceVSAvoidsignal transmission characteristic

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by creating a non-uniform metal pattern distribution. The open region is strategically positioned to remove metal only where it creates harmful capacitance with non-contact bumps, while maintaining metal patterns in other areas for electrical connectivity. This localized modification optimizes signal integrity without compromising overall package functionality.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent extracts the harmful capacitive effect by creating an open region that removes metal patterns from specific areas. This extraction eliminates the parasitic capacitance between non-contact bumps and adjacent metal layers, thereby removing the source of impedance discontinuity while preserving the necessary electrical connections through contact pads.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12622296B2Semiconductor package including metal pattern layer with open region which overlaps non-contact pad

Publication Date: 2026.05.05 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes: a package substrate including a plurality of insulating layers and a plurality of metal pattern layers respectively disposed on the plurality of insulating layers, wherein each of the plurality of metal pattern layers has an interconnection layer; at least one semiconductor chip disposed on an upper surface of the package substrate, and connected to the interconnection layer; contact pads disposed on a lower surface of the package substrate, and connected to the interconnection layer; and non-contact pads disposed on the lower surface of the package substrate, and insulated from the interconnection layer, wherein a lowermost metal pattern layer among the plurality of metal pattern layers has a first open region at least partially overlapping at least one non-contact pad among the non-contact pads, in a direction perpendicular to the upper surface of the package substrate.