Semiconductor Package Planarization Layer for Redistribution Reliability
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Solution Overview
Problem
The increasing density and functionality of semiconductor dies pose challenges in packaging, particularly in manufacturing, as existing technologies struggle to efficiently integrate and connect a high number of I/O pads effectively.
Innovation Solution
A package structure is formed using a temporary adhesive layer, where the integrated circuit dies are partially sunk into and surrounded by a package layer, and a planarization layer is deposited to fill the gap left after the adhesive layer's removal, allowing for a flat surface for forming a patterned redistribution layer that enhances reliability and flexibility in I/O connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a temporary adhesive layer is used to support high-density I/O dies during packaging, then the die placement and connection density can be improved, but step gaps are formed after adhesive removal that cause redistribution layer cracks and reduce reliability
Solution Approach 1:
The patent applies preliminary action by forming the planarization layer during the packaging process before the redistribution layer is created. This planarization layer pre-fills the step gaps that would otherwise form after adhesive removal, ensuring a flat surface is ready for redistribution layer deposition and preventing subsequent cracking.
Solution Approach 2:
The patent introduces a planarization layer as an intermediary element between the package layer and the redistribution layer. This intermediate layer mediates the structural transition, filling the step gaps and providing mechanical support to prevent redistribution layer cracks while maintaining the benefits of temporary adhesive layer usage.
2Ease of manufacture
If the adhesive layer is removed after die placement, then the temporary carrier can be discarded and cost reduced, but step gaps are created that compromise structural integrity
Solution Approach 1:
The patent extracts the temporary adhesive layer from the final package structure, allowing it to be removed after serving its purpose during die placement. This extraction enables the use of inexpensive temporary carriers while maintaining final package strength through the planarization layer that compensates for the adhesive layer's removal.
Solution Approach 2:
The planarization layer is formed in advance to pre-compensate for the structural void that will be created when the adhesive layer is removed. This preliminary structural preparation ensures that when the adhesive layer is extracted, the package structure maintains its integrity without step gaps.
3Reliability
If a flat surface is required for redistribution layer formation, then connection reliability improves, but additional processing steps are needed to achieve planarity
Solution Approach 1:
The patent merges the planarization function with the packaging process itself. The planarization layer is formed as part of the package structure during the same processing sequence, combining the structural support function with the surface flattening function in a single integrated process rather than requiring separate planarization steps.
Solution Approach 2:
The patent changes the physical state and properties of the planarization layer material to achieve planarity. By selecting materials with appropriate viscosity, fill characteristics, and curing properties, the planarization layer automatically flows and levels to create a flat surface during the packaging process, eliminating the need for mechanical planing or polishing steps.
Data Source
AI summary
Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.