Package Structure With Recessed Covering Layer For Wiring
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Solution Overview
Problem
Current electronic packaging technologies face challenges in maximizing spatial utilization and reducing wiring length and density as electronic components continue to miniaturize, with Through Silicon Via (TSV) processes being limited in reducing wiring length to millimeter scales.
Innovation Solution
A package structure and manufacturing method that utilizes a substrate with varying electronic component heights, forming a covering layer with recesses and exposing conductive contacts, and a wiring layer that covers these recesses and contacts to enable flexible wiring layouts, reducing the overall area required on the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If Through Silicon Via (TSV) stacking is used to economize space and reduce wiring length, then spatial utilization is improved, but wiring length reduction is limited to millimeter scale only
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by forming wiring layers above the substrate surface using vertical vias through the substrate. This dimensional change allows wiring to extend in the vertical direction (Z-axis) rather than only in the horizontal plane, significantly reducing wiring length and enabling finer pitch interconnections that overcome the millimeter-scale limitation of conventional TSV stacking.
2Volume of moving object
If electronic components are miniaturized to increase distribution density, then spatial utilization is improved, but system processing speed and stability may be compromised
Solution Approach 1:
The patent implements localized wiring structures with different characteristics in different regions. Specifically, it creates first wiring regions with first wiring layers and second wiring regions with second wiring layers, allowing each region to be optimized for its specific function. This local quality approach enables miniaturization while maintaining reliability by providing dedicated wiring paths and isolation for different circuit functions, preventing interference and ensuring stable operation despite reduced component sizes.
3Area of stationary object
If wiring density is increased to accommodate more connections in smaller area, then spatial utilization is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the wiring structure into multiple distinct wiring layers (first wiring layer, second wiring layer) and divides the substrate into different wiring regions. This segmentation allows complex wiring functions to be distributed across multiple simpler layers, making the manufacturing process more manageable. Each wiring layer can be formed and patterned independently, reducing the overall manufacturing complexity compared to attempting to create all connections in a single dense layer.
Data Source
AI summary
A package structure comprises a substrate, a plurality of first electronic components, at least a second electronic component, a first covering layer and a wiring layer. A surface of the substrate includes a first region and a second region. The first electronic components are disposed in the first region, wherein at least one of the first electronic components has a first conductive contact. The second electronic component is disposed in the second region. The first covering layer includes a recess and a first exposing region for exposing the first conductive contact. The wiring layer is formed on the recess and electronically coupled to the first conductive contact.