Semiconductor Package Spacer Trenches to Prevent Stack Interface Peeling
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Solution Overview
Problem
The challenge of interface peeling phenomena between lower and upper chip stacks in semiconductor packages due to the use of epoxy molding compounds, which occurs when multiple semiconductor chips are stacked within a limited package area, necessitating improved reliability in chip stacking arrangements.
Innovation Solution
A semiconductor package design featuring a substrate with spaced semiconductor chip stacks, a spacer with trenches, and a mold layer that covers the chip stacks and spacer, enhancing contact area and minimizing interface peeling by using a concavo-convex structure and varying trench gaps to stabilize the chip stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked within a limited package area, then the chip density and integration are improved, but interface peeling occurs between chip stacks reducing reliability
Solution Approach 1:
The spacer is segmented into multiple regions with different trench gap widths, creating zones of varying mechanical constraint. This segmentation allows the structure to accommodate thermal expansion differences while maintaining overall structural integrity, preventing interface peeling between chip stacks.
Solution Approach 2:
Different regions of the spacer are designed with locally optimized trench gap widths - narrower gaps in regions requiring stronger mechanical coupling and wider gaps in regions needing thermal expansion accommodation. This local quality variation optimizes both bonding strength and stress management at different locations.
2Ease of manufacture
If a spacer with uniform trench gap is used between chip stacks, then manufacturing simplicity is maintained, but interface peeling occurs due to insufficient stress management
Solution Approach 1:
The spacer incorporates regions with different trench gap widths to locally optimize stress distribution and thermal expansion management. This local variation in geometry provides enhanced interface stability without significantly complicating the manufacturing process.
Solution Approach 2:
The trench gap width parameter is varied across different regions of the spacer to optimize mechanical and thermal performance. By changing this geometric parameter locally, the design achieves better stress management and interface bonding while maintaining a relatively simple overall structure.
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a substrate; a plurality of first semiconductor chips on the substrate and spaced apart from each other in a first direction; a plurality of second semiconductor chips on the plurality of first semiconductor chips; a spacer between an uppermost one of the plurality of first semiconductor chips and a lowermost one of the plurality of second semiconductor chips, a plurality of trenches extending in the first direction; and a mold layer within the plurality of trenches.