Semiconductor Package Strengthening Layer for Chip Stability
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Solution Overview
Problem
Existing semiconductor package structures face issues with semiconductor chip steadiness due to uneven etching, position shifting, and vulnerability to deformation and damage during fabrication, particularly with the etching process causing damage to metal layers.
Innovation Solution
A package structure comprising a dielectric layer with through holes, a strengthening layer, and solder mask layers to support the semiconductor chip, with surface treatment and encapsulant to maintain steadiness and prevent damage, using electroplating or chemical plating for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the disposing trough and troughs are fabricated during an etching process, then the package structure can be formed, but the bottoms become uneven causing unsteadiness and position shifting of the semiconductor chip
Solution Approach 1:
The invention divides the support structure into two separate components: a planarization layer that provides a flat bottom surface, and a reinforcing layer that provides structural strength. This segmentation allows each layer to perform its specific function independently, solving the contradiction between ease of manufacture and manufacturing precision.
Solution Approach 2:
The planarization layer is formed before the semiconductor chip is mounted, creating a pre-flattened surface that ensures even contact and prevents position shifting. This preliminary action of surface planarization resolves the issue of uneven bottoms caused by the etching process.
2Ease of operation
If the copper substrate is removed to expose metal layers, then external connections are enabled, but more etching time is required causing damages on the metal layers
Solution Approach 1:
The invention changes the thickness parameter of the copper substrate to an optimized range (50-200 micrometers) that allows for shorter etching times. This parameter optimization enables the removal of the copper substrate without requiring excessive etching time that would damage the metal layers, thus maintaining reliability while enabling external connections.
3Device complexity
If the semiconductor chip is disposed in the disposing trough, then the package structure is formed, but the chip experiences unsteadiness and position shifting
Solution Approach 1:
The invention uses a composite structure consisting of a planarization layer (providing flat surface) and a reinforcing layer (providing mechanical strength) to create a stable mounting surface. This composite approach ensures chip steadiness without significantly increasing device complexity, as both layers can be integrated into the existing package structure.
4Ease of manufacture
If the package body has no strengthened construction, then the fabrication process is simpler, but the package body is easily deformed due to external force
Solution Approach 1:
The reinforcing layer serves multiple functions: it strengthens the package body to resist external forces, provides mechanical support for the semiconductor chip, and can be integrated with the existing fabrication process. This multi-functionality approach enhances strength without significantly complicating the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures the semiconductor chip remains steady without position shifting, prevents damage to wire bonding pads, and enhances electrical connection quality by maintaining even surfaces and reducing etching time, thereby improving the structural integrity and electrical performance.
Implementation Method 1
using electroplating or chemical plating for enhanced connectivity
Implementation Method 2
using electroplating or chemical plating for enhanced connectivity
Data Source
AI summary
A package structure is provided, which includes a dielectric layer having opposing first and second surfaces, and through holes penetrating the surfaces; a strengthening layer formed on the first surface; a circuit layer formed on the second surface, and having wire bonding pads formed thereon and exposed from the through holes, and ball pads electrically connected to the wire bonding pads; a first solder mask layer formed on the first surface and the strengthening layer, and having first apertures formed therethrough for exposing the wire bonding pads; a second solder mask layer formed on the second surface and the circuit layer, and having second apertures formed therethrough for exposing the ball pads; and a semiconductor chip disposed on the first solder mask layer and electrically connected via conductive wires to the wire bonding pads exposed from the through holes. The strengthening layer ensures the steadiness of the chip to be mounted thereon without position shifting.