Semiconductor Package Structure With Stress Buffer for Die Singulation

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The challenges in semiconductor packaging include the delamination of dielectric layers due to debris and stress from laser grooving processes, leading to reduced yield and reliability in 3D packaging.

Innovation Solution

A stress buffer layer is introduced to wrap the debris layer formed during laser grooving, using a polymer material with lower Young's modulus than the dielectric layer to absorb stress and prevent delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If laser grooving process is used to singulate semiconductor dies, then productivity is improved, but delamination of dielectric layers occurs due to debris and stress

Engineering Contradiction:

Improvesingulation efficiencyVSAvoiddielectric layer adhesion

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A protective layer is introduced as an intermediary between the debris layer and the dielectric layer. This protective layer prevents direct contact between the debris and dielectric layer, eliminating the delamination issue while preserving the benefits of laser grooving for high-productivity singulation

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful debris generated during laser grooving is converted into a beneficial structure by forming a protective layer over it. The debris layer, which originally caused delamination, becomes part of a multi-layer structure where the protective layer prevents harm, allowing the debris to remain in place without causing reliability issues

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Adaptability or versatility

If package size is reduced to meet smaller component demands, then adaptability is improved, but manufacturing precision becomes more difficult

Engineering Contradiction:

Improvepackage size adaptabilityVSAvoidfabrication difficulty

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The protective layer is formed beforehand before subsequent packaging processes. This preliminary action prevents delamination issues from arising in the first place, enabling precise manufacturing even in reduced-size packages where margin for error is minimal

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stress buffer layer effectively reduces delamination issues, improving the reliability and yield of the package structure by absorbing stress from moisture absorption and maintaining structural integrity.

Implementation Method 1

absorbing stress from moisture absorption

Methodology Applied

Scientific EffectMoisture absorption: Absorption (physical)

Implementation Method 2

performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening

Methodology Applied

Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS12599029B2Package structure and method of forming the same

Publication Date: 2026.04.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.