Package Substrate Embedded Semiconductor Component Via Formation
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Solution Overview
Problem
Conventional semiconductor package substrates require complex and costly processes to form expanded pads and conductive vias, increasing manufacturing time and complexity.
Innovation Solution
A package substrate design where a semiconductor chip is embedded with a passivation layer having openings for electrode pads, and vias are formed by laser drilling through a thermosetting dielectric layer and polyimide passivation layer, allowing direct electrical connection and reducing process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If adhesion layer and protection layer are formed before dicing, then subsequent processes are facilitated, but exposed portions must be removed before lamination increasing manufacturing time and cost
Solution Approach 1:
The patent applies preliminary action by forming the adhesion layer and protection layer on the wafer before dicing into chips. This allows subsequent lamination and via formation processes to be performed more easily, while the layers are subsequently removed only where needed after the chips are mounted, avoiding the need to remove entire exposed portions before lamination.
Solution Approach 2:
The patent segments the removal process by selectively removing the adhesion layer and protection layer only in specific regions after chip mounting, rather than removing all exposed portions. This is achieved by forming a mask layer that protects certain areas during removal, thereby reducing manufacturing time and material waste.
2Manufacturing precision
If expanded pads and conductive vias are formed separately, then alignment is facilitated, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the formation of expanded pads and conductive vias into a single integrated process. The mask layer is formed to define both the expanded pad regions and the via holes simultaneously, allowing both structures to be created in one lamination and etching cycle, thereby reducing manufacturing complexity while maintaining alignment precision through the unified mask pattern.
3Reliability
If multiple layers are formed and removed, then electrical connection is achieved, but process steps and costs increase
Solution Approach 1:
The patent extracts and removes only the necessary portions of the adhesion layer and protection layer after chip mounting, rather than removing entire layers. By using a selectively formed mask layer, the process removes material only where needed for via formation and pad expansion, reducing the number of process steps and improving manufacturing efficiency while maintaining reliable electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces manufacturing costs and time by simplifying the process of forming conductive vias directly connected to electrode pads, while protecting the semiconductor chip from oxidation and damage.
Implementation Method 1
a plurality of vias are formed by laser drilling through a thermosetting dielectric layer and polyimide passivation layer
Data Source
AI summary
A package substrate embedded with a semiconductor component includes a substrate, a semiconductor chip, a first dielectric layer, a first circuit layer and first conductive vias. The substrate is formed with an opening for allowing the semiconductor chip to be secured therein. The semiconductor chip has an active surface and an inactive surface, wherein a plurality of electrode pads are formed on the active surface thereof and a passivation layer disposed thereon. The first dielectric layer is disposed both on the substrate and the passivation layer, wherein vias are formed at locations corresponding to those of the electrode pads and penetrating the dielectric layer and the passivation layer to expose the electrode pads therefrom. The first circuit layer is disposed on the first dielectric layer and electrically connected to the first conductive vias. The first conductive vias are disposed in the openings of the dielectric and passivation layers and the first circuit layer is electrically connected to the electrode pads, thereby allowing the first conductive vias to be electrically connected to the electrode pads of the chip.