Package Substrate Groove Depth Uniformity via Shaping Layer

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Solution Overview

Problem

Conventional semiconductor package substrates face issues with non-uniform groove depths due to micro-etching of the first circuit layers during metal layer removal, leading to poor solder ball bonding reliability and signal transmission integrity.

Innovation Solution

A package substrate design featuring a shaping layer with a material different from the first circuit layer, allowing for uniform groove depths when the shaping layer is removed, thereby preventing side etching and ensuring effective solder ball embedding and signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the first circuit layer is micro-etched when the metal layer is removed by etching, then the metal layer can be completely removed, but the groove depths become non-uniform and the first circuit layer is damaged

Engineering Contradiction:
Improvesolder ball bonding reliabilityVSAvoidgroove depth uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A shaping layer is introduced as an intermediary between the metal layer and the first circuit layer. This shaping layer serves as a protective barrier during the etching process, preventing direct contact between the etching solution and the first circuit layer, thereby avoiding side etching and depth non-uniformity while allowing complete metal layer removal

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The shaping layer is formed in advance before the etching process. This preliminary formation of the shaping layer creates a protective structure that guides the etching process and prevents damage to the first circuit layer during subsequent metal layer removal, ensuring uniform groove depths

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the line width/line spacing of the first circuit layer is designed toward miniaturization, then the integration density is improved, but the first circuit layer is more likely to be disconnected by side etching

Engineering Contradiction:
Improveintegration densityVSAvoidsignal transmission integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The shaping layer acts as a protective intermediary that shields the miniaturized first circuit layer from side etching during metal layer removal. This protection is crucial for maintaining the integrity of fine-line circuits with small line widths and tight spacing, preventing disconnection while enabling high integration density

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The shaping layer is formed in advance to prevent side etching before it can damage the first circuit layer. This preliminary protective action counteracts the harmful effect of etching on miniaturized circuit structures, allowing aggressive etching parameters to be used without compromising circuit integrity

Inventive Principle:
Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution achieves uniform groove depths, enhancing solder ball bonding reliability and preventing signal transmission disruptions, thus improving the overall reliability and enabling mass production of miniaturized package substrates.

Implementation Method 1

copper is electroplated on the dielectric layer 12 and in the blind holes 120 to form a second circuit layer 13 on the dielectric layer 12

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS20250159800A1Package substrate and manufacturing method thereof
Publication Date: 2025.05.15 AALTOSEMI INC
  • US20250159800A1 patent drawing
  • US20250159800A1 patent drawing
  • US20250159800A1 patent drawing

AI summary

A package substrate is provided, in which a plurality of grooves are formed on a dielectric layer, so that a first circuit layer is embedded in the dielectric layer and is exposed from the grooves, wherein the depths of the plurality of grooves are uniform to facilitate embedding a plurality of solder balls in the plurality of grooves and bonding the plurality of solder balls to the first circuit layer.